diff --git a/src/cache/cache.sv b/src/cache/cache.sv index da7f83276..56044384b 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -96,8 +96,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE logic [LINELEN-1:0] ReadDataLine, ReadDataLineCache; logic SelFetchBuffer; logic CacheEn; - logic [CACHEWORDSPERLINE-1:0] MemPAdrDecoded; - logic [LINELEN/8-1:0] LineByteMask, DemuxedByteMask, FetchBufferByteSel; + logic [LINELEN/8-1:0] LineByteMask; logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1:0] WordOffsetAddr; genvar index; @@ -161,21 +160,30 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE ///////////////////////////////////////////////////////////////////////////////////////////// // Write Path ///////////////////////////////////////////////////////////////////////////////////////////// + if(!READ_ONLY_CACHE) begin:WriteSelLogic + logic [CACHEWORDSPERLINE-1:0] MemPAdrDecoded; + logic [LINELEN/8-1:0] DemuxedByteMask, FetchBufferByteSel; - // Adjust byte mask from word to cache line - onehotdecoder #(LOGCWPL) adrdec(.bin(PAdr[LOGCWPL+LOGLLENBYTES-1:LOGLLENBYTES]), .decoded(MemPAdrDecoded)); - for(index = 0; index < 2**LOGCWPL; index++) begin - assign DemuxedByteMask[(index+1)*(WORDLEN/8)-1:index*(WORDLEN/8)] = MemPAdrDecoded[index] ? ByteMask : '0; - end - assign FetchBufferByteSel = SetValid & ~SetDirty ? '1 : ~DemuxedByteMask; // If load miss set all muxes to 1. - assign LineByteMask = SetValid ? '1 : SetDirty ? DemuxedByteMask : '0; + // Adjust byte mask from word to cache line + onehotdecoder #(LOGCWPL) adrdec(.bin(PAdr[LOGCWPL+LOGLLENBYTES-1:LOGLLENBYTES]), .decoded(MemPAdrDecoded)); + for(index = 0; index < 2**LOGCWPL; index++) begin + assign DemuxedByteMask[(index+1)*(WORDLEN/8)-1:index*(WORDLEN/8)] = MemPAdrDecoded[index] ? ByteMask : '0; + end + assign FetchBufferByteSel = SetValid & ~SetDirty ? '1 : ~DemuxedByteMask; // If load miss set all muxes to 1. - // Merge write data into fetched cache line for store miss - for(index = 0; index < LINELEN/8; index++) begin - mux2 #(8) WriteDataMux(.d0(CacheWriteData[(8*index)%WORDLEN+7:(8*index)%WORDLEN]), - .d1(FetchBuffer[8*index+7:8*index]), .s(FetchBufferByteSel[index]), .y(LineWriteData[8*index+7:8*index])); + // Merge write data into fetched cache line for store miss + for(index = 0; index < LINELEN/8; index++) begin + mux2 #(8) WriteDataMux(.d0(CacheWriteData[(8*index)%WORDLEN+7:(8*index)%WORDLEN]), + .d1(FetchBuffer[8*index+7:8*index]), .s(FetchBufferByteSel[index]), .y(LineWriteData[8*index+7:8*index])); + end + assign LineByteMask = SetValid ? '1 : SetDirty ? DemuxedByteMask : '0; end - + else + begin:WriteSelLogic + // No need for this mux if the cache does not handle writes. + assign LineWriteData = FetchBuffer; + assign LineByteMask = '1; + end ///////////////////////////////////////////////////////////////////////////////////////////// // Flush logic ///////////////////////////////////////////////////////////////////////////////////////////// diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index 05e26f4bf..780807943 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -98,7 +98,9 @@ module cacheLRU assign LRUUpdate[t1] = LRUUpdate[s] & WayEncoded[r]; end - mux2 #(1) LRUMuxes[NUMWAYS-2:0](CurrLRU, ~WayExpanded, LRUUpdate, NextLRU); + // The root node of the LRU tree will always be selected in LRUUpdate. No mux needed. + assign NextLRU[NUMWAYS-2] = ~WayExpanded[NUMWAYS-2]; + mux2 #(1) LRUMuxes[NUMWAYS-3:0](CurrLRU[NUMWAYS-3:0], ~WayExpanded[NUMWAYS-3:0], LRUUpdate[NUMWAYS-3:0], NextLRU[NUMWAYS-3:0]); // Compute next victim way. for(s = NUMWAYS-2; s >= NUMWAYS/2; s--) begin @@ -128,8 +130,8 @@ module cacheLRU always_ff @(posedge clk) begin if (reset) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0; if(CacheEn) begin - if((InvalidateCache | FlushCache) & ~FlushStage) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0; - else if (LRUWriteEn & ~FlushStage) begin + // if((InvalidateCache | FlushCache) & ~FlushStage) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0; + if (LRUWriteEn & ~FlushStage) begin LRUMemory[PAdr] <= NextLRU; end if(LRUWriteEn & ~FlushStage & (PAdr == CacheSet)) diff --git a/src/ifu/decompress.sv b/src/ifu/decompress.sv index 0ab0e706a..b28a9e7be 100644 --- a/src/ifu/decompress.sv +++ b/src/ifu/decompress.sv @@ -135,10 +135,16 @@ module decompress ( IllegalCompInstrD = 1; InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap end + // coverage off + // are excluding this branch from coverage because in rv64gc XLEN is always 64 and thus greater than 32 bits + // This branch will only be taken if instr16[12:10] == 3'b111 and 'XLEN !> 32, because all other + // possible values for instr16[12:10] are covered by branches above. XLEN !> 32 + // will never occur in rv64gc so this branch can not be covered else begin // illegal instruction IllegalCompInstrD = 1; InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap end + // coverage on 5'b01101: InstrD = {immCJ, 5'b00000, 7'b1101111}; // c.j 5'b01110: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011}; // c.beqz 5'b01111: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b001, immCB[4:0], 7'b1100011}; // c.bnez diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S index 3fdca6e84..a349ac606 100644 --- a/tests/coverage/fpu.S +++ b/tests/coverage/fpu.S @@ -57,6 +57,23 @@ main: fcvt.l.q a0, ft3 fcvt.lu.q a0, ft3 + + // Tests verfying that half and quad floating point convertion instructions are not supported by rv64gc + # fcvt.h.d ft3, ft0 // Somehow this instruction is taking the route on line 124 + // idea: enable the Q extension for this to work properly? A: Q and halfs not supported in rv64gc + # fcvt.h.w ft3, a0 + # fcvt.w.h a0, ft0 + # fcvt.q.w ft3, a0 + # fcvt.w.q a0, ft0 + # fcvt.q.d ft3, ft0 + + .word 0x38007553 // Testing the all False case for 119 - funct7 under, op = 101 0011 + .word 0x40000053 // Line 145 All False Test case - illegal instruction? + .word 0xd0400053 // Line 156 All False Test case - illegal instruction? + .word 0xc0400053 // Line 162 All False Test case - illegal instruction? + .word 0xd2400053 // Line 168 All False Test case - illegal instruction? + .word 0xc2400053 // Line 174 All False Test case - illegal instruction? + # Test illegal instructions are detected .word 0x00000007 // illegal floating-point load (bad Funct3) .word 0x00000027 // illegal floating-point store (bad Funct3) diff --git a/tests/coverage/ifu.S b/tests/coverage/ifu.S index 3ceeeac12..9cde14ce2 100644 --- a/tests/coverage/ifu.S +++ b/tests/coverage/ifu.S @@ -32,9 +32,23 @@ main: csrs mstatus, t0 # calling compressed floating point load double instruction - //.halfword 0x2000 // CL type compressed floating-point ld-->funct3,imm,rs1',imm,rd',op + //.hword 0x2000 // CL type compressed floating-point ld-->funct3,imm,rs1',imm,rd',op // binary version 0000 0000 0000 0000 0010 0000 0000 0000 mv s0, sp c.fld fs0, 0(s0) + c.fsd fs0, 0(s0) + + // c.fldsp fs0, 0 + .hword 0x2002 + + // c.fsdsp fs0, 0 + .hword 0xA002 + + //# Illegal compressed instruction with op = 01, instr[15:10] = 100111, and 0's everywhere else + //.hword 0x9C01 + + # Line Illegal compressed instruction + .hword 0x9C41 + j done diff --git a/tests/coverage/priv.S b/tests/coverage/priv.S index 008d06be6..c4e9e302d 100644 --- a/tests/coverage/priv.S +++ b/tests/coverage/priv.S @@ -36,11 +36,6 @@ main: addi t0, zero, 0 csrr t0, stimecmp - # CSR coverage - csrw scause, zero - csrw stval, zero - csrw scounteren, zero - csrw satp, zero # satp write with mstatus.TVM = 1 bseti t0, zero, 20 @@ -62,4 +57,58 @@ main: + # Test write to STVAL, SCAUSE, SEPC, and STIMECMP CSRs + li t0, 0 + csrw stval, t0 + csrw scause, t0 + csrw sepc, t0 + csrw stimecmp, t0 + csrw scounteren, zero + csrw satp, zero + + + # Switch to machine mode + li a0, 3 + ecall + # Testing the HPMCOUNTERM performance counter: writing + # Base address is 2816 (MHPMCOUNTERBASE) + # There are 32 HPMCOUNTER registers + csrw 2816, t0 + csrw 2817, t0 + csrw 2818, t0 + csrw 2819, t0 + csrw 2820, t0 + csrw 2821, t0 + csrw 2822, t0 + csrw 2823, t0 + csrw 2824, t0 + csrw 2825, t0 + csrw 2826, t0 + csrw 2827, t0 + csrw 2828, t0 + csrw 2829, t0 + csrw 2830, t0 + csrw 2831, t0 + csrw 2832, t0 + csrw 2833, t0 + csrw 2834, t0 + csrw 2835, t0 + csrw 2836, t0 + csrw 2837, t0 + csrw 2838, t0 + csrw 2839, t0 + csrw 2840, t0 + csrw 2841, t0 + csrw 2842, t0 + csrw 2843, t0 + csrw 2844, t0 + csrw 2845, t0 + csrw 2846, t0 + csrw 2847, t0 + + # Testing the HPMCOUNTERM performance counter: reading + csrr t0, 2817 j done + + +