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Improved comment.

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This commit is contained in:
Ross Thompson 2023-01-19 17:41:57 -06:00
parent 91bd55d9ba
commit 63dbebcb5a
1 changed files with 3 additions and 3 deletions
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6
pipelined/src/generic/mem/ram1p1rwbe.sv
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@ -64,13 +64,13 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) (
end else begin: ram end else begin: ram
integer i; integer i;
// Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff.
// Therefore these always blocks use the older always @(posedge clk)
// Read // Read
always @(posedge clk) always_ff @(posedge clk)
if(ce) dout <= #1 RAM[addr]; if(ce) dout <= #1 RAM[addr];
// Write divided into part for bytes and part for extra msbs // Write divided into part for bytes and part for extra msbs
// Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff.
// Therefore these always blocks use the older always @(posedge clk)
if(WIDTH >= 8) if(WIDTH >= 8)
always @(posedge clk) always @(posedge clk)
if (ce & we) if (ce & we)