Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Pushed vcu118 to 71MHz.

Browse Source
This commit is contained in:
Ross Thompson 2023-08-25 17:04:50 -05:00
parent 7c6db7de85
commit 63c9c3a1a8
3 changed files with 10 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
fpga/constraints/constraints-vcu118.xdc
View File

@ -117,10 +117,10 @@ set_property PULLUP true [get_ports {SDCCmd}]
set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.500 [get_ports {SDCDat[*]}]
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 21.000 [get_ports {SDCDat[*]}]
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 10.000 [get_ports {SDCDat[*]}]
set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.500 [get_ports {SDCCmd}]
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 14.000 [get_ports {SDCCmd}]
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 10.000 [get_ports {SDCCmd}]
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {SDCCmd}]

2
fpga/generator/xlnx_ddr4-vcu118.tcl
View File

@ -38,7 +38,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
CONFIG.C0.DDR4_AxiNarrowBurst {false} \
CONFIG.Reference_Clock {Differential} \
CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {50} \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {71} \
CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \
CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \

16
linux/devicetree/wally-vcu118.dts
View File

@ -9,20 +9,20 @@
chosen {
linux,initrd-end = <0x85c43a00>;
linux,initrd-start = <0x84200000>;
bootargs = "root=/dev/vda ro";
bootargs = "root=/dev/vda ro console=ttyS0,115200";
stdout-path = "/soc/uart@10000000";
};
memory@80000000 {
device_type = "memory";
reg = <0x00 0x80000000 0x00 0x08000000>;
reg = <0x00 0x80000000 0x00 0x10000000>;
};
cpus {
#address-cells = <0x01>;
#size-cells = <0x00>;
clock-frequency = <0x2FAF080>;
timebase-frequency = <0x2FAF080>;
clock-frequency = <0x43B5FC0>;
timebase-frequency = <0x43B5FC0>;
cpu@0 {
phandle = <0x01>;
@ -51,7 +51,7 @@
uart@10000000 {
interrupts = <0x0a>;
interrupt-parent = <0x03>;
clock-frequency = <0x2FAF080>;
clock-frequency = <0x43B5FC0>;
reg = <0x00 0x10000000 0x00 0x100>;
compatible = "ns16550a";
};
@ -74,10 +74,8 @@
fifo-depth = <256>;
bus-width = <4>;
interrupt-parent = <0x03>;
clock = <0x2FAF080>;
max-frequency = <0x989680>;
cap-sd-highspeed;
cap-mmc-highspeed;
clock = <0x43B5FC0>;
max-frequency = <0xF4240>;
no-sdio;
};