From 63c7c18771ad4ecd7eeda0d4664bb9a275066307 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sun, 7 Feb 2021 23:28:21 -0500
Subject: [PATCH] Fixed lw by delaying read value by one cycle

---
 wally-pipelined/src/ebu/ahblite.sv | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv
index 9d4e62be7..55f79cebc 100644
--- a/wally-pipelined/src/ebu/ahblite.sv
+++ b/wally-pipelined/src/ebu/ahblite.sv
@@ -32,6 +32,7 @@
 
 module ahblite (
   input  logic             clk, reset,
+  input  logic             StallW, FlushW,
   // Load control
   input  logic             UnsignedLoadM,
   // Signals from Instruction Cache
@@ -71,7 +72,7 @@ module ahblite (
 
   logic GrantData;
   logic [2:0] ISize;
-  logic [`AHBW-1:0] HRDATAMasked;
+  logic [`AHBW-1:0] HRDATAMasked, ReadDataM;
   logic IReady, DReady;
 //  logic [3:0] HSIZED; // size delayed by one cycle for reads
 //  logic [2:0] HADDRD; // address delayed for subword reads
@@ -136,7 +137,9 @@ module ahblite (
   // *** assumes AHBW = XLEN
   assign InstrRData = HRDATAMasked[31:0];
   assign IReady = HREADY & InstrReadF & ~GrantData; // maybe unused?***
-  assign ReadDataW = HRDATAMasked;
+//  assign ReadDataW = HRDATAMasked;
+  assign ReadDataM = HRDATAMasked; // changed from W to M dh 2/7/2021
+  flopenrc #(`XLEN) ReadDataWReg(clk, reset, FlushW, ~StallW, ReadDataM, ReadDataW);
   assign DReady = HREADY & GrantData; // ***unused?