From 637cc3b78a6c004a08356c08fc9b4dc6aa3d8fbd Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 6 Nov 2023 14:11:42 -0800 Subject: [PATCH] Reparitioned sign logic in fdivsqrt to match paper --- src/fpu/fdivsqrt/fdivsqrt.sv | 6 +++--- src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 6 ++++-- src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 8 +++----- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/src/fpu/fdivsqrt/fdivsqrt.sv b/src/fpu/fdivsqrt/fdivsqrt.sv index 9112da9d1..5c5fa0f57 100644 --- a/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/src/fpu/fdivsqrt/fdivsqrt.sv @@ -68,7 +68,7 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) ( logic BZeroM; // Denominator is zero logic IntDivM; // Integer operation logic [P.DIVBLEN:0] nM, mM; // Shift amounts - logic NegQuotM, ALTBM, AsM, W64M; // Special handling for postprocessor + logic ALTBM, AsM, BsM, W64M; // Special handling for postprocessor logic [P.XLEN-1:0] AM; // Original Numerator for postprocessor logic ISpecialCaseE; // Integer div/remainder special cases @@ -78,7 +78,7 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) ( // Int-specific .ForwardedSrcAE, .ForwardedSrcBE, .IntDivE, .W64E, .ISpecialCaseE, .BZeroM, .nM, .mM, .AM, - .IntDivM, .W64M, .NegQuotM, .ALTBM, .AsM); + .IntDivM, .W64M, .ALTBM, .AsM, .BsM); fdivsqrtfsm #(P) fdivsqrtfsm( // FSM .clk, .reset, .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, @@ -96,6 +96,6 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) ( .SqrtE, .Firstun, .SqrtM, .SpecialCaseM, .QmM, .WZeroE, .DivStickyM, // Int-specific - .nM, .mM, .ALTBM, .AsM, .BZeroM, .NegQuotM, .W64M, .RemOpM(Funct3M[1]), .AM, + .nM, .mM, .ALTBM, .AsM, .BsM, .BZeroM, .W64M, .RemOpM(Funct3M[1]), .AM, .FIntDivResultM); endmodule diff --git a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index 19856e932..c3c558902 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -34,9 +34,9 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) ( input logic [P.DIVb:0] FirstU, FirstUM, input logic [P.DIVb+1:0] FirstC, input logic SqrtE, - input logic Firstun, SqrtM, SpecialCaseM, NegQuotM, + input logic Firstun, SqrtM, SpecialCaseM, input logic [P.XLEN-1:0] AM, - input logic RemOpM, ALTBM, BZeroM, AsM, W64M, + input logic RemOpM, ALTBM, BZeroM, AsM, BsM, W64M, input logic [P.DIVBLEN:0] nM, mM, output logic [P.DIVb:0] QmM, output logic WZeroE, @@ -49,6 +49,7 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) ( logic NegStickyM; logic weq0E, WZeroM; logic [P.XLEN-1:0] IntDivResultM; + logic NegQuotM; // Integer quotient is negative ////////////////////////// // Execute Stage: Detect early termination for an exact result @@ -103,6 +104,7 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) ( assign UnsignedQuotM = {3'b000, PreQmM}; // Integer remainder: sticky and sign correction muxes + assign NegQuotM = AsM ^ BsM; // Integer Quotient is negative mux2 #(P.DIVb+4) normremdmux(W, W+D, NegStickyM, NormRemDM); mux2 #(P.DIVb+4) normremsmux(NormRemDM, -NormRemDM, AsM, NormRemM); mux2 #(P.DIVb+4) quotresmux(UnsignedQuotM, -UnsignedQuotM, NegQuotM, NormQuotM); diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 5e14d3122..6c397576a 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -43,8 +43,8 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( output logic ISpecialCaseE, output logic [P.DURLEN-1:0] CyclesE, output logic [P.DIVBLEN:0] nM, mM, - output logic NegQuotM, ALTBM, IntDivM, W64M, - output logic AsM, BZeroM, + output logic ALTBM, IntDivM, W64M, + output logic AsM, BsM, BZeroM, output logic [P.XLEN-1:0] AM ); @@ -57,7 +57,6 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( logic NumerZeroE; // Numerator is zero (X or A) logic AZeroE, BZeroE; // A or B is Zero for integer division logic SignedDivE; // signed division - logic NegQuotE; // Integer quotient is negative logic AsE, BsE; // Signs of integer inputs logic [P.XLEN-1:0] AE; // input A after W64 adjustment logic ALTBE; @@ -84,7 +83,6 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( assign BZeroE = ~(|BE); assign AsE = AE[P.XLEN-1] & SignedDivE; assign BsE = BE[P.XLEN-1] & SignedDivE; - assign NegQuotE = AsE ^ BsE; // Integer Quotient is negative // Force integer inputs to be postiive mux2 #(P.XLEN) posamux(AE, -AE, AsE, PosA); @@ -192,9 +190,9 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( // pipeline registers flopen #(1) mdureg(clk, IFDivStartE, IntDivE, IntDivM); flopen #(1) altbreg(clk, IFDivStartE, ALTBE, ALTBM); - flopen #(1) negquotreg(clk, IFDivStartE, NegQuotE, NegQuotM); flopen #(1) bzeroreg(clk, IFDivStartE, BZeroE, BZeroM); flopen #(1) asignreg(clk, IFDivStartE, AsE, AsM); + flopen #(1) bsignreg(clk, IFDivStartE, BsE, BsM); flopen #(P.DIVBLEN+1) nreg(clk, IFDivStartE, nE, nM); flopen #(P.DIVBLEN+1) mreg(clk, IFDivStartE, mE, mM); flopen #(P.XLEN) srcareg(clk, IFDivStartE, AE, AM);