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Removed comment about nonexistent possible bug

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David Harris 2022-11-14 09:56:33 -08:00
parent 06dbed92c8
commit 6372139af4
1 changed files with 0 additions and 1 deletions
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pipelined/src/mmu/hptw.sv
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@ -223,7 +223,6 @@ module hptw (
if (`XLEN == 32) begin if (`XLEN == 32) begin
assign InitialWalkerState = L1_ADR; assign InitialWalkerState = L1_ADR;
assign MegapageMisaligned = |(CurrentPPN[9:0]); // must have zero PPN0 assign MegapageMisaligned = |(CurrentPPN[9:0]); // must have zero PPN0
// *** Possible bug - should be L1_ADR? If so, applies to 64 bits as well
assign Misaligned = ((WalkerState == L0_ADR) & MegapageMisaligned); assign Misaligned = ((WalkerState == L0_ADR) & MegapageMisaligned);
end else begin end else begin
logic GigapageMisaligned, TerapageMisaligned; logic GigapageMisaligned, TerapageMisaligned;