diff --git a/wally-pipelined/regression/wally-peripherals.do b/wally-pipelined/regression/wally-peripherals.do index d9d9daa37..d0df00fb9 100644 --- a/wally-pipelined/regression/wally-peripherals.do +++ b/wally-pipelined/regression/wally-peripherals.do @@ -39,70 +39,4 @@ vopt +acc work.testbench -o workopt vsim workopt view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively -add wave /testbench/clk -add wave /testbench/reset -add wave -divider -add wave /testbench/dut/hart/ebu/IReadF -add wave /testbench/dut/hart/DataStall -add wave /testbench/dut/hart/InstrStall -add wave /testbench/dut/hart/StallF -add wave /testbench/dut/hart/StallD -add wave /testbench/dut/hart/FlushD -add wave /testbench/dut/hart/FlushE -add wave /testbench/dut/hart/FlushM -add wave /testbench/dut/hart/FlushW - -add wave -divider -add wave -hex /testbench/dut/hart/ifu/PCF -add wave -hex /testbench/dut/hart/ifu/InstrF -add wave /testbench/InstrFName -#add wave -hex /testbench/dut/hart/ifu/PCD -add wave -hex /testbench/dut/hart/ifu/InstrD -add wave /testbench/InstrDName -add wave -divider -#add wave -hex /testbench/dut/hart/ifu/PCE -#add wave -hex /testbench/dut/hart/ifu/InstrE -add wave /testbench/InstrEName -add wave -hex /testbench/dut/hart/ieu/dp/SrcAE -add wave -hex /testbench/dut/hart/ieu/dp/SrcBE -add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE -add wave /testbench/dut/hart/ieu/dp/PCSrcE -add wave -divider -#add wave -hex /testbench/dut/hart/ifu/PCM -#add wave -hex /testbench/dut/hart/ifu/InstrM -add wave /testbench/InstrMName -add wave /testbench/dut/uncore/dtim/memwrite -add wave -hex /testbench/dut/uncore/HADDR -add wave -hex /testbench/dut/uncore/HWDATA -add wave -divider -add wave -hex /testbench/dut/hart/ifu/PCW -add wave /testbench/InstrWName -add wave /testbench/dut/hart/ieu/dp/RegWriteW -add wave -hex /testbench/dut/hart/ieu/dp/ResultW -add wave -hex /testbench/dut/hart/ieu/dp/RdW -add wave -divider -add wave -hex /testbench/dut/uncore/uart/u/* -add wave -divider -#add ww -add wave -hex -r /testbench/* - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {100 ps} -configure wave -namecolwidth 250 -configure wave -valuecolwidth 120 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -set DefaultRadix hexadecimal - --- Run the Simulation -run 5000 -#run -all -#quit +do wally-peripherals-signals.do diff --git a/wally-pipelined/src/uncore/clint.sv b/wally-pipelined/src/uncore/clint.sv index 215ef7df0..71770323e 100644 --- a/wally-pipelined/src/uncore/clint.sv +++ b/wally-pipelined/src/uncore/clint.sv @@ -28,8 +28,9 @@ module clint ( input logic HCLK, HRESETn, - input logic [1:0] MemRWclint, - input logic [15:0] HADDR, + input logic HSELCLINT, + input logic [15:0] HADDR, + input logic HWRITE, input logic [`XLEN-1:0] HWDATA, output logic [`XLEN-1:0] HREADCLINT, output logic HRESPCLINT, HREADYCLINT, @@ -41,8 +42,8 @@ module clint ( logic [15:0] entry; logic memread, memwrite; - assign memread = MemRWclint[1]; - assign memwrite = MemRWclint[0]; + assign memread = HSELCLINT & ~HWRITE; + assign memwrite = HSELCLINT & HWRITE; assign HRESPCLINT = 0; // OK // assign HREADYCLINT = 1; // Respond immediately always_ff @(posedge HCLK) // delay response diff --git a/wally-pipelined/src/uncore/dtim.sv b/wally-pipelined/src/uncore/dtim.sv index 6f53c4c51..42ae7fbcc 100644 --- a/wally-pipelined/src/uncore/dtim.sv +++ b/wally-pipelined/src/uncore/dtim.sv @@ -27,22 +27,28 @@ module dtim #(parameter BASE=0, RANGE = 65535) ( input logic HCLK, HRESETn, - input logic [1:0] MemRWtim, - input logic [31:0] HADDR, - input logic [`XLEN-1:0] HWDATA, input logic HSELTim, + input logic [31:0] HADDR, + input logic HWRITE, + input logic [`XLEN-1:0] HWDATA, output logic [`XLEN-1:0] HREADTim, output logic HRESPTim, HREADYTim ); logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE+BASE)>>1+(`XLEN/32)]; - logic [31:0] HWADDR; + logic [31:0] HWADDR, A; logic [`XLEN-1:0] HREADTim0; // logic [`XLEN-1:0] write; logic [15:0] entry; - logic memread, memwrite; - logic [3:0] busycount; + logic memread, memwrite; + logic [3:0] busycount; + + always_ff @(posedge HCLK) begin + memread <= HSELTim & ~ HWRITE; + memwrite <= HSELTim & HWRITE; + A <= HADDR; + end // busy FSM to extend READY signal always_ff @(posedge HCLK, negedge HRESETn) @@ -61,41 +67,20 @@ module dtim #(parameter BASE=0, RANGE = 65535) ( end end - /* always_ff @(posedge HCLK, negedge HRESETn) - if (~HRESETn) begin - HREADYTim <= 0; - end else begin - HREADYTim <= HSELTim; // always respond one cycle later - end */ - - - assign memread = MemRWtim[1]; - assign memwrite = MemRWtim[0]; -// always_ff @(posedge HCLK) -// memwrite <= MemRWtim[0]; // delay memwrite to write phase assign HRESPTim = 0; // OK -// assign HREADYTim = 1; // Respond immediately; *** extend this - // Model memory read and write - generate if (`XLEN == 64) begin -// always_ff @(negedge HCLK) -// if (memwrite) RAM[HWADDR[31:3]] <= HWDATA; always_ff @(posedge HCLK) begin - //if (memwrite) RAM[HADDR[31:3]] <= HWDATA; - HWADDR <= HADDR; - HREADTim0 <= RAM[HADDR[31:3]]; + HWADDR <= A; + HREADTim0 <= RAM[A[31:3]]; if (memwrite && HREADYTim) RAM[HWADDR[31:3]] <= HWDATA; end end else begin -// always_ff @(negedge HCLK) -// if (memwrite) RAM[HWADDR[31:2]] <= HWDATA; always_ff @(posedge HCLK) begin - //if (memwrite) RAM[HADDR[31:2]] <= HWDATA; - HWADDR <= HADDR; - HREADTim0 <= RAM[HADDR[31:2]]; + HWADDR <= A; + HREADTim0 <= RAM[A[31:2]]; if (memwrite && HREADYTim) RAM[HWADDR[31:2]] <= HWDATA; end end diff --git a/wally-pipelined/src/uncore/gpio.sv b/wally-pipelined/src/uncore/gpio.sv index ffea6c72e..216e30ddf 100644 --- a/wally-pipelined/src/uncore/gpio.sv +++ b/wally-pipelined/src/uncore/gpio.sv @@ -29,9 +29,10 @@ module gpio ( input logic HCLK, HRESETn, - input logic [1:0] MemRWgpio, + input logic HSELGPIO, input logic [7:0] HADDR, input logic [`XLEN-1:0] HWDATA, + input logic HWRITE, output logic [`XLEN-1:0] HREADGPIO, output logic HRESPGPIO, HREADYGPIO, input logic [31:0] GPIOPinsIn, @@ -42,8 +43,8 @@ module gpio ( logic [7:0] entry; logic memread, memwrite; - assign memread = MemRWgpio[1]; - assign memwrite = MemRWgpio[0]; + assign memread = HSELGPIO & ~HWRITE; + assign memwrite = HSELGPIO & HWRITE; assign HRESPGPIO = 0; // OK always_ff @(posedge HCLK) // delay response to data cycle HREADYGPIO <= memread | memwrite; diff --git a/wally-pipelined/src/uncore/uart.sv b/wally-pipelined/src/uncore/uart.sv index b4854981a..373674867 100644 --- a/wally-pipelined/src/uncore/uart.sv +++ b/wally-pipelined/src/uncore/uart.sv @@ -29,8 +29,9 @@ module uart ( input logic HCLK, HRESETn, - input logic [1:0] MemRWuart, - input logic [2:0] HADDR, + input logic HSELUART, + input logic [2:0] HADDR, + input logic HWRITE, input logic [`XLEN-1:0] HWDATA, output logic [`XLEN-1:0] HREADUART, output logic HRESPUART, HREADYUART, @@ -44,37 +45,37 @@ module uart ( logic [7:0] Din, Dout; // rename processor interface signals to match PC16550D and provide one-byte interface - assign MEMRb = ~MemRWuart[1]; - assign MEMWb = ~MemRWuart[0]; - assign A = HADDR[2:0]; + always_ff @(posedge HCLK) begin + MEMRb <= ~(HSELUART & ~HWRITE); + MEMWb <= ~(HSELUART & HWRITE); + A <= HADDR[2:0]; + end assign HRESPUART = 0; // OK - //assign HREADYUART = 1; // Respond immediately - always_ff @(posedge HCLK) // delay response to data cycle - HREADYUART <= ~MEMRb | ~MEMWb; + assign HREADYUART = 1; // should idle high during address phase and respond high when done; will need to be modified if UART ever needs more than 1 cycle to do something generate if (`XLEN == 64) begin - always @(posedge HCLK) begin + always_comb begin HREADUART = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout}; - case (HADDR) - 3'b000: Din <= HWDATA[7:0]; - 3'b001: Din <= HWDATA[15:8]; - 3'b010: Din <= HWDATA[23:16]; - 3'b011: Din <= HWDATA[31:24]; - 3'b100: Din <= HWDATA[39:32]; - 3'b101: Din <= HWDATA[47:40]; - 3'b110: Din <= HWDATA[55:48]; - 3'b111: Din <= HWDATA[63:56]; + case (A) + 3'b000: Din = HWDATA[7:0]; + 3'b001: Din = HWDATA[15:8]; + 3'b010: Din = HWDATA[23:16]; + 3'b011: Din = HWDATA[31:24]; + 3'b100: Din = HWDATA[39:32]; + 3'b101: Din = HWDATA[47:40]; + 3'b110: Din = HWDATA[55:48]; + 3'b111: Din = HWDATA[63:56]; endcase end end else begin // 32-bit - always @(posedge HCLK) begin + always_comb begin HREADUART = {Dout, Dout, Dout, Dout}; - case (HADDR[1:0]) - 2'b00: Din <= HWDATA[7:0]; - 2'b01: Din <= HWDATA[15:8]; - 2'b10: Din <= HWDATA[23:16]; - 2'b11: Din <= HWDATA[31:24]; + case (A[1:0]) + 2'b00: Din = HWDATA[7:0]; + 2'b01: Din = HWDATA[15:8]; + 2'b10: Din = HWDATA[23:16]; + 2'b11: Din = HWDATA[31:24]; endcase end end diff --git a/wally-pipelined/src/uncore/uartPC16550D.sv b/wally-pipelined/src/uncore/uartPC16550D.sv index d494e19f2..28b530751 100644 --- a/wally-pipelined/src/uncore/uartPC16550D.sv +++ b/wally-pipelined/src/uncore/uartPC16550D.sv @@ -376,7 +376,7 @@ module uartPC16550D( TXHR <= Din; txhrfull <= 1; end - $display("UART transmits: %c",Din); // for testbench + $write("%c",Din); // for testbench end if (txstate == UART_IDLE) begin // move data into tx shift register if available if (fifoenabled) begin diff --git a/wally-pipelined/src/uncore/uncore.sv b/wally-pipelined/src/uncore/uncore.sv index 77ed3ff5c..a46ca6ba3 100644 --- a/wally-pipelined/src/uncore/uncore.sv +++ b/wally-pipelined/src/uncore/uncore.sv @@ -2,7 +2,7 @@ // uncore.sv // // Written: David_Harris@hmc.edu 9 January 2021 -// Modified: +// Modified: Ben Bracker 6 Mar 2021 to better fit AMBA 3 AHB-Lite spec // // Purpose: System-on-Chip components outside the core (hart) // Memories, peripherals, external bus control @@ -59,14 +59,14 @@ module uncore ( logic [`XLEN-1:0] HWDATA; logic [`XLEN-1:0] HREADTim, HREADCLINT, HREADGPIO, HREADUART; + logic HSELTim, HSELCLINT, HSELGPIO, PreHSELUART, HSELUART; + logic HSELTimD, HSELCLINTD, HSELGPIOD, HSELUARTD; logic HRESPTim, HRESPCLINT, HRESPGPIO, HRESPUART; logic HREADYTim, HREADYCLINT, HREADYGPIO, HREADYUART; - logic [1:0] MemRW; - logic [1:0] MemRWtim, MemRWclint, MemRWgpio, MemRWuart; `ifdef BOOTTIMBASE logic [`XLEN-1:0] HREADBootTim; - logic HSELBootTim, HRESPBootTim, HREADYBootTim; + logic HSELBootTim, HSELBootTimD, HRESPBootTim, HREADYBootTim; logic [1:0] MemRWboottim; `endif logic UARTIntr;// *** will need to tie INTR to an interrupt handler @@ -95,13 +95,6 @@ module uncore ( assign MemRWgpio = MemRW & {2{HSELGPIO}}; `endif assign MemRWuart = MemRW & {2{HSELUART}}; -/* always_ff @(posedge HCLK) begin - HADDRD <= HADDR; - MemRWtim <= MemRW & {2{HSELTim}}; - MemRWclint <= MemRW & {2{HSELCLINT}}; - MemRWgpio <= MemRW & {2{HSELGPIO}}; - MemRWuart <= MemRW & {2{HSELUART}}; - end */ // subword accesses: converts HWDATAIN to HWDATA subwordwrite sww(.*); @@ -120,45 +113,57 @@ module uncore ( `endif uart uart(.HADDR(HADDR[2:0]), .TXRDYb(), .RXRDYb(), .INTR(UARTIntr), .SIN(UARTSin), .SOUT(UARTSout), .DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1), - .RTSb(), .DTRb(), .OUT1b(), .OUT2b(), .*); + .RTSb(), .DTRb(), .OUT1b(), .OUT2b(), .*); // mux could also include external memory // AHB Read Multiplexer - assign HRDATA = ({`XLEN{HSELTim}} & HREADTim) | ({`XLEN{HSELCLINT}} & HREADCLINT) | + assign HRDATA = ({`XLEN{HSELTimD}} & HREADTim) | ({`XLEN{HSELCLINTD}} & HREADCLINT) | `ifdef GPIOBASE - ({`XLEN{HSELGPIO}} & HREADGPIO) | + ({`XLEN{HSELGPIOD}} & HREADGPIO) | `endif `ifdef BOOTTIMBASE - ({`XLEN{HSELBootTim}} & HREADBootTim) | + ({`XLEN{HSELBootTimD}} & HREADBootTim) | `endif - ({`XLEN{HSELUART}} & HREADUART); - assign HRESP = HSELTim & HRESPTim | HSELCLINT & HRESPCLINT | + ({`XLEN{HSELUARTD}} & HREADUART); + assign HRESP = HSELTimD & HRESPTim | HSELCLINTD & HRESPCLINT | `ifdef GPIOBASE - HSELGPIO & HRESPGPIO | + HSELGPIOD & HRESPGPIO | `endif `ifdef BOOTTIMBASE - HSELBootTim & HRESPBootTim | + HSELBootTimD & HRESPBootTim | `endif - HSELUART & HRESPUART; - assign HREADY = HSELTim & HREADYTim | HSELCLINT & HREADYCLINT | + HSELUARTD & HRESPUART; + assign HREADY = HSELTimD & HREADYTim | HSELCLINTD & HREADYCLINT | `ifdef GPIOBASE - HSELGPIO & HREADYGPIO | + HSELGPIOD & HREADYGPIO | `endif `ifdef BOOTTIMBASE - HSELBootTim & HREADYBootTim | + HSELBootTimD & HREADYBootTim | `endif - HSELUART & HREADYUART; + HSELUARTD & HREADYUART; // Faults - assign DataAccessFaultM = ~(HSELTim | HSELCLINT | + assign DataAccessFaultM = ~(HSELTimD | HSELCLINTD | `ifdef GPIOBASE - HSELGPIO | + HSELGPIOD | `endif `ifdef BOOTTIMBASE - HSELBootTim | + HSELBootTimD | `endif - HSELUART); + HSELUARTD); - + + // Synchronized Address Decoder (figure 4-2 in spec) + always_ff @(posedge HCLK) begin + HSELTimD <= HSELTim; + HSELCLINTD <= HSELCLINT; + `ifdef GPIOBASE + HSELGPIOD <= HSELGPIO; + `endif + HSELUARTD <= HSELUART; + `ifdef BOOTTIMBASE + HSELBootTimD <= HSELBootTim; + `endif + end endmodule