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https://github.com/openhwgroup/cvw
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Adding stalls for memory delays
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9c81278f28
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@ -35,17 +35,17 @@ module ahblite (
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// Load control
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// Load control
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input logic UnsignedLoadM,
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input logic UnsignedLoadM,
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// Signals from Instruction Cache
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// Signals from Instruction Cache
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input logic [`XLEN-1:0] IPAdrD,
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input logic [`XLEN-1:0] IPAdrF,
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input logic IReadD,
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input logic IReadF,
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output logic [`XLEN-1:0] IRData,
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output logic [`XLEN-1:0] IRData,
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output logic IReady,
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// output logic IReady,
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// Signals from Data Cache
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// Signals from Data Cache
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input logic [`XLEN-1:0] DPAdrM,
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input logic [`XLEN-1:0] DPAdrM,
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input logic DReadM, DWriteM,
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input logic DReadM, DWriteM,
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input logic [`XLEN-1:0] DWDataM,
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input logic [`XLEN-1:0] DWDataM,
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input logic [1:0] DSizeM,
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input logic [1:0] DSizeM,
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output logic [`XLEN-1:0] DRData,
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output logic [`XLEN-1:0] DRData,
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output logic DReady,
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// output logic DReady,
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// AHB-Lite external signals
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// AHB-Lite external signals
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input logic [`AHBW-1:0] HRDATA,
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input logic [`AHBW-1:0] HRDATA,
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input logic HREADY, HRESP,
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input logic HREADY, HRESP,
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@ -57,12 +57,15 @@ module ahblite (
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output logic [2:0] HBURST,
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output logic [2:0] HBURST,
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output logic [3:0] HPROT,
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output logic [3:0] HPROT,
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output logic [1:0] HTRANS,
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output logic [1:0] HTRANS,
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output logic HMASTLOCK
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output logic HMASTLOCK,
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// Stalls
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output logic InstrStall, DataStall
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);
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);
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logic GrantData;
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logic GrantData;
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logic [2:0] ISize;
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logic [2:0] ISize;
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logic [`AHBW-1:0] HRDATAMasked;
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logic [`AHBW-1:0] HRDATAMasked;
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logic IReady, DReady;
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assign HCLK = clk;
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assign HCLK = clk;
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assign HRESETn = ~reset;
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assign HRESETn = ~reset;
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@ -79,22 +82,28 @@ module ahblite (
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endgenerate
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endgenerate
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// drive bus outputs
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// drive bus outputs
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assign HADDR = GrantData ? DPAdrM[31:0] : IPAdrD[31:0];
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assign HADDR = GrantData ? DPAdrM[31:0] : IPAdrF[31:0];
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assign HWDATA = DWDataM;
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assign HWDATA = DWDataM;
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//flop #(`XLEN) wdreg(HCLK, DWDataM, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
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//flop #(`XLEN) wdreg(HCLK, DWDataM, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
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assign HWRITE = DWriteM;
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assign HWRITE = DWriteM;
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assign HSIZE = GrantData ? {1'b0, DSizeM} : ISize;
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assign HSIZE = GrantData ? {1'b0, DSizeM} : ISize;
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assign HBURST = 3'b000; // Single burst only supported; consider generalizing for cache fillsfHPROT
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assign HBURST = 3'b000; // Single burst only supported; consider generalizing for cache fillsfHPROT
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assign HPROT = 4'b0011; // not used; see Section 3.7
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assign HPROT = 4'b0011; // not used; see Section 3.7
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assign HTRANS = IReadD | DReadM | DWriteM ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise
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assign HTRANS = IReadF | DReadM | DWriteM ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise
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assign HMASTLOCK = 0; // no locking supported
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assign HMASTLOCK = 0; // no locking supported
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// Route signals to Instruction and Data Caches
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// Route signals to Instruction and Data Caches
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// *** assumes AHBW = XLEN
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// *** assumes AHBW = XLEN
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assign IRData = HRDATAMasked;
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assign IRData = HRDATAMasked;
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assign IReady = HREADY & IReadD & ~GrantData;
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assign IReady = HREADY & IReadF & ~GrantData; // maybe unused?***
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assign DRData = HRDATAMasked;
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assign DRData = HRDATAMasked;
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assign DReady = HREADY & GrantData;
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assign DReady = HREADY & GrantData; // ***unused?
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// stalls
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// Stall MEM stage if data is being accessed and bus isn't yet ready
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assign DataStall = GrantData & ~HREADY;
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// Stall Fetch stage if instruction should be read but reading data or bus isn't ready
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assign InstrStall = IReadF & (GrantData | ~HREADY);
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// *** consider adding memory access faults based on HRESP being high
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// *** consider adding memory access faults based on HRESP being high
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// InstrAccessFaultF, DataAccessFaultM,
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// InstrAccessFaultF, DataAccessFaultM,
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@ -42,7 +42,6 @@ module dcu (
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output logic StoreMisalignedFaultM, StoreAccessFaultM
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output logic StoreMisalignedFaultM, StoreAccessFaultM
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);
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);
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// memdp memdp(.*);
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// Determine if an Unaligned access is taking place
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// Determine if an Unaligned access is taking place
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always_comb
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always_comb
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@ -39,11 +39,35 @@ module dtim (
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// logic [`XLEN-1:0] write;
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// logic [`XLEN-1:0] write;
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logic [15:0] entry;
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logic [15:0] entry;
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logic memread, memwrite;
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logic memread, memwrite;
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// logic busy;
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logic [3:0] busycount;
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// busy FSM to extend READY signal
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always_ff @(posedge HCLK, negedge HRESETn)
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if (~HRESETn) begin
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// busy <= 0;
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HREADYTim <= 1;
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end else begin
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// if (~busy & HSELTim) begin
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if (HREADYTim & HSELTim) begin
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// busy <= 1;
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busycount <= 0;
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HREADYTim <= 0;
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// end else if (busy) begin
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end else if (~HREADYTim) begin
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busycount <= busycount + 1;
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if (busycount == 4) begin // TIM latency, for testing purposes
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// busy <= 0;
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HREADYTim <= 1;
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end
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end
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end
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assign memread = MemRWtim[1];
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assign memread = MemRWtim[1];
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assign memwrite = MemRWtim[0];
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assign memwrite = MemRWtim[0];
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assign HRESPTim = 0; // OK
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assign HRESPTim = 0; // OK
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assign HREADYTim = 1; // Respond immediately; *** extend this
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// assign HREADYTim = 1; // Respond immediately; *** extend this
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// word aligned reads
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// word aligned reads
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generate
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generate
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@ -29,6 +29,7 @@ module hazard(
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input logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW,
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input logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW,
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input logic PCSrcE, MemReadE,
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input logic PCSrcE, MemReadE,
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input logic RegWriteM, RegWriteW, CSRWritePendingDEM, RetM, TrapM,
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input logic RegWriteM, RegWriteW, CSRWritePendingDEM, RetM, TrapM,
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input logic InstrStall, DataStall,
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output logic [1:0] ForwardAE, ForwardBE,
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output logic [1:0] ForwardAE, ForwardBE,
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output logic StallF, StallD, FlushD, FlushE, FlushM, FlushW,
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output logic StallF, StallD, FlushD, FlushE, FlushM, FlushW,
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output logic LoadStallD);
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output logic LoadStallD);
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@ -54,11 +55,24 @@ module hazard(
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// Exceptions: flush entire pipeline
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// Exceptions: flush entire pipeline
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// Ret instructions: occur in M stage. Might be possible to move earlier, but be careful about hazards
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// Ret instructions: occur in M stage. Might be possible to move earlier, but be careful about hazards
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// General stall and flush rules:
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// A stage must stall if the next stage is stalled
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// If any stages are stalled, the first stage that isn't stalled must flush.
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assign LoadStallD = MemReadE & ((Rs1D == RdE) | (Rs2D == RdE));
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assign LoadStallD = MemReadE & ((Rs1D == RdE) | (Rs2D == RdE));
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assign StallD = LoadStallD;
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assign StallD = LoadStallD;
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assign StallF = LoadStallD | CSRWritePendingDEM;
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assign StallF = StallD | InstrStall | CSRWritePendingDEM;
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assign FlushD = PCSrcE | CSRWritePendingDEM | RetM | TrapM;
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assign FlushD = PCSrcE |InstrStall | CSRWritePendingDEM | RetM | TrapM;
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assign FlushE = LoadStallD | PCSrcE | RetM | TrapM;
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assign FlushE = LoadStallD | PCSrcE | RetM | TrapM;
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assign FlushM = RetM | TrapM;
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assign FlushM = RetM | TrapM;
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assign FlushW = TrapM;
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assign FlushW = TrapM;
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/*
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assign LoadStallD = MemReadE & ((Rs1D == RdE) | (Rs2D == RdE));
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assign StallD = LoadStallD;
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assign StallF = StallD | CSRWritePendingDEM;
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assign FlushD = PCSrcE | CSRWritePendingDEM | RetM | TrapM;
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assign FlushE = LoadStallD | PCSrcE | RetM | TrapM;
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assign FlushM = RetM | TrapM;
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assign FlushW = TrapM; */
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endmodule
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endmodule
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@ -87,16 +87,17 @@ module wallypipelinedhart (
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logic [2:0] Funct3M;
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logic [2:0] Funct3M;
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logic [`XLEN-1:0] DataAdrM, WriteDataM;
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logic [`XLEN-1:0] DataAdrM, WriteDataM;
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logic [`XLEN-1:0] ReadDataM;
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logic [`XLEN-1:0] ReadDataM;
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logic DataStall, InstrStall;
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ifu ifu(.*); // instruction fetch unit: PC, branch prediction, instruction cache
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ifu ifu(.*); // instruction fetch unit: PC, branch prediction, instruction cache
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ieu ieu(.*); // inteber execution unit: integer register file, datapath and controller
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ieu ieu(.*); // inteber execution unit: integer register file, datapath and controller
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dcu dcu(/*.Funct3M(InstrM[14:12]),*/ .*); // data cache unit
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dcu dcu(/*.Funct3M(InstrM[14:12]),*/ .*); // data cache unit
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ahblite ebu(
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ahblite ebu( // *** make IRData InstrF
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.IPAdrD(zero), .IReadD(1'b0), .IRData(), .IReady(),
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.IPAdrF(PCF), .IReadF(1'b0), .IRData(), //.IReady(),
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.DPAdrM(DataAdrM), .DReadM(MemRWdcuoutM[1]), .DWriteM(MemRWdcuoutM[0]), .DWDataM(WriteDataM),
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.DPAdrM(DataAdrM), .DReadM(MemRWdcuoutM[1]), .DWriteM(MemRWdcuoutM[0]), .DWDataM(WriteDataM),
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.DSizeM(Funct3M[1:0]), .DRData(ReadDataM), .DReady(),
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.DSizeM(Funct3M[1:0]), .DRData(ReadDataM), //.DReady(),
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.UnsignedLoadM(Funct3M[2]),
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.UnsignedLoadM(Funct3M[2]),
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.*);
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.*);
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// assign UnsignedLoadM = Funct3M[2]; // *** maybe move read extension to dcu
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// assign UnsignedLoadM = Funct3M[2]; // *** maybe move read extension to dcu
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