From 61c714ebe6e65885f728da5e3f22be5b085d8ac0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 25 Mar 2022 13:10:31 -0500 Subject: [PATCH] I think this version of csri matches what is required in the spec. ExtIntS should not be written into the SEIP register bit. --- pipelined/src/privileged/csri.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/privileged/csri.sv b/pipelined/src/privileged/csri.sv index 7eff94962..b9a302d2a 100644 --- a/pipelined/src/privileged/csri.sv +++ b/pipelined/src/privileged/csri.sv @@ -58,7 +58,7 @@ module csri #(parameter always_comb begin IntInM = 0; IntInM[11] = ExtIntM; // MEIP - IntInM[9] = ExtIntS | (ExtIntM & MIDELEG_REGW[9]); // SEIP + IntInM[9] = (ExtIntM & MIDELEG_REGW[9]); // SEIP IntInM[7] = TimerIntM; // MTIP IntInM[5] = TimerIntM & MIDELEG_REGW[5]; // STIP IntInM[3] = SwIntM; // MSIP