From 61c5d035e9cf3f6e6bebb24598867e767a993a2c Mon Sep 17 00:00:00 2001
From: Jordan Carlin <jordanmcarlin@gmail.com>
Date: Thu, 14 Nov 2024 15:03:13 -0800
Subject: [PATCH] Add mseccfg shell to wallyTracer and reformat CSRs

---
 testbench/common/wallyTracer.sv | 453 ++++++++++++++++++++------------
 1 file changed, 290 insertions(+), 163 deletions(-)

diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv
index b4bf68a36..7f8e43cdd 100644
--- a/testbench/common/wallyTracer.sv
+++ b/testbench/common/wallyTracer.sv
@@ -122,8 +122,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
     // ensure the CSR is detected when the pipeline's Writeback stage is not
     // stalled.  If it is stalled we want CSRArray to hold the old value.
     if(valid) begin 
-      // machine CSRs    
-      // PMPCFG  space is 0-15 3a0 - 3af
+      // PMPCFG CSRs (space is 0-15 3a0 - 3af)
       int inc = P.XLEN == 32 ? 4 : 8;
       int i, i4, i8, csrid;
       logic [P.XLEN-1:0] pmp;
@@ -145,7 +144,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
         CSRArray[csrid] = pmp;
       end
 
-      // PMPADDR space is 0-63 3b0 - 3ef
+      // PMPADDR CSRs (space is 0-63 3b0 - 3ef)
       for (i=0; i<P.PMP_ENTRIES; i++) begin
         pmp = testbench.dut.core.priv.priv.csr.csrm.PMPADDR_ARRAY_REGW[i];
         
@@ -153,50 +152,69 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
         CSRArray[csrid] = pmp;
       end
 
+      // M-mode trap CSRs
       CSRArray[12'h300] = testbench.dut.core.priv.priv.csr.csrm.MSTATUS_REGW;
-      CSRArray[12'h305] = testbench.dut.core.priv.priv.csr.csrm.MTVEC_REGW;
-      CSRArray[12'h341] = testbench.dut.core.priv.priv.csr.csrm.MEPC_REGW;
-      CSRArray[12'h306] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW;
-      CSRArray[12'h320] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW;
       CSRArray[12'h302] = testbench.dut.core.priv.priv.csr.csrm.MEDELEG_REGW;
       CSRArray[12'h303] = testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW;
-      CSRArray[12'h344] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW;
       CSRArray[12'h304] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW;
-      CSRArray[12'h301] = testbench.dut.core.priv.priv.csr.csrm.MISA_REGW;
-      CSRArray[12'h30A] = testbench.dut.core.priv.priv.csr.csrm.MENVCFG_REGW;
-      CSRArray[12'hF14] = testbench.dut.core.priv.priv.csr.csrm.MHARTID_REGW;
+      CSRArray[12'h305] = testbench.dut.core.priv.priv.csr.csrm.MTVEC_REGW;
       CSRArray[12'h340] = testbench.dut.core.priv.priv.csr.csrm.MSCRATCH_REGW;
+      CSRArray[12'h341] = testbench.dut.core.priv.priv.csr.csrm.MEPC_REGW;
       CSRArray[12'h342] = testbench.dut.core.priv.priv.csr.csrm.MCAUSE_REGW;
       CSRArray[12'h343] = testbench.dut.core.priv.priv.csr.csrm.MTVAL_REGW;
-      CSRArray[12'hF11] = 0;
-      CSRArray[12'hF12] = 0;
-      CSRArray[12'hF13] = {{P.XLEN-12{1'b0}}, 12'h100}; //P.XLEN'h100;
-      CSRArray[12'hF15] = 0;
-      CSRArray[12'h34A] = 0;
-      // MCYCLE and MINSTRET
-      CSRArray[12'hB00] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0];
-      CSRArray[12'hB02] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];
-      // supervisor CSRs
+      CSRArray[12'h344] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW;
+      
+      // S-mode trap CSRs
       CSRArray[12'h100] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW;
       CSRArray[12'h104] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222;
       CSRArray[12'h105] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW;
-      CSRArray[12'h141] = testbench.dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW;
-      CSRArray[12'h106] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW;
-      CSRArray[12'h10A] = testbench.dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW;
-      CSRArray[12'h180] = testbench.dut.core.priv.priv.csr.csrs.csrs.SATP_REGW;
       CSRArray[12'h140] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW;
-      CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW;
+      CSRArray[12'h141] = testbench.dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW;
       CSRArray[12'h142] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW;
+      CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW;
       CSRArray[12'h144] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW;
-      CSRArray[12'h14D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[P.XLEN-1:0];
-      // user CSRs
+
+      // Virtual Memory CSRs
+      CSRArray[12'h180] = testbench.dut.core.priv.priv.csr.csrs.csrs.SATP_REGW;
+
+      // Floating-Point CSRs
       CSRArray[12'h001] = testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW;
       CSRArray[12'h002] = testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW;
       CSRArray[12'h003] = {testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW};
 
+      // Counters / Performance Monitoring CSRs
+      CSRArray[12'h306] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW;
+      CSRArray[12'h106] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW;
+      CSRArray[12'h320] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW;
+      // mhpmevent3-31 not connected (232-33F)
+      CSRArray[12'hB00] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0]; // MCYCLE
+      CSRArray[12'hB02] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]; // MINSTRET
+      // mhpmcounter3-31 not connected (B03-B1F)
+      // cycle, time, instret not connected (C00-C02)
+      // hpmcounter3-31 not connected (C03-C1F)
+
+      // Machine Information Registers and Configuration CSRs
+      CSRArray[12'h301] = testbench.dut.core.priv.priv.csr.csrm.MISA_REGW;
+      CSRArray[12'h30A] = testbench.dut.core.priv.priv.csr.csrm.MENVCFG_REGW;
+      CSRArray[12'h10A] = testbench.dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW;
+      CSRArray[12'h747] = 0; // mseccfg
+      CSRArray[12'hF11] = 0; //mvendorid
+      CSRArray[12'hF12] = 0; // marchid
+      CSRArray[12'hF13] = {{P.XLEN-12{1'b0}}, 12'h100}; // mimpid
+      CSRArray[12'hF14] = testbench.dut.core.priv.priv.csr.csrm.MHARTID_REGW;
+      CSRArray[12'hF15] = 0; //mconfigptr
+
+      // Sstc CSRs
+      CSRArray[12'h14D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[P.XLEN-1:0];
+      
+      // Zkr CSRs
+      // seed not connected (015)
+
+      // extra CSRs for RV32
       if (P.XLEN == 32) begin
         CSRArray[12'h310] = testbench.dut.core.priv.priv.csr.csrsr.MSTATUSH_REGW;
         CSRArray[12'h31A] = testbench.dut.core.priv.priv.csr.csrm.MENVCFGH_REGW;
+        CSRArray[12'h757] = 0; // mseccfgh
         CSRArray[12'h15D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[63:32];
       end
     end else begin // hold the old value if the pipeline is stalled.
@@ -208,50 +226,69 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
       for(csrid='h3B0; csrid<='h3EF; csrid++)
         CSRArray[csrid] = CSRArrayOld[csrid];
 
+      // M-mode trap CSRs
       CSRArray[12'h300] = CSRArrayOld[12'h300];
-      CSRArray[12'h305] = CSRArrayOld[12'h305];
-      CSRArray[12'h341] = CSRArrayOld[12'h341];
-      CSRArray[12'h306] = CSRArrayOld[12'h306];
-      CSRArray[12'h320] = CSRArrayOld[12'h320];
       CSRArray[12'h302] = CSRArrayOld[12'h302];
       CSRArray[12'h303] = CSRArrayOld[12'h303];
-      CSRArray[12'h344] = CSRArrayOld[12'h344];
       CSRArray[12'h304] = CSRArrayOld[12'h304];
-      CSRArray[12'h301] = CSRArrayOld[12'h301];
-      CSRArray[12'h30A] = CSRArrayOld[12'h30A];
-      CSRArray[12'hF14] = CSRArrayOld[12'hF14];
+      CSRArray[12'h305] = CSRArrayOld[12'h305];
       CSRArray[12'h340] = CSRArrayOld[12'h340];
+      CSRArray[12'h341] = CSRArrayOld[12'h341];
       CSRArray[12'h342] = CSRArrayOld[12'h342];
       CSRArray[12'h343] = CSRArrayOld[12'h343];
-      CSRArray[12'hF11] = CSRArrayOld[12'hF11];
-      CSRArray[12'hF12] = CSRArrayOld[12'hF12];
-      CSRArray[12'hF13] = CSRArrayOld[12'hF13];
-      CSRArray[12'hF15] = CSRArrayOld[12'hF15];
-      CSRArray[12'h34A] = CSRArrayOld[12'h34A];
-      // MCYCLE and MINSTRET
-      CSRArray[12'hB00] = CSRArrayOld[12'hB00];
-      CSRArray[12'hB02] = CSRArrayOld[12'hB02];
-      // supervisor CSRs
+      CSRArray[12'h344] = CSRArrayOld[12'h344];
+
+      // S-mode trap CSRs
       CSRArray[12'h100] = CSRArrayOld[12'h100];
       CSRArray[12'h104] = CSRArrayOld[12'h104];
       CSRArray[12'h105] = CSRArrayOld[12'h105];
-      CSRArray[12'h141] = CSRArrayOld[12'h141];
-      CSRArray[12'h106] = CSRArrayOld[12'h106];
-      CSRArray[12'h10A] = CSRArrayOld[12'h10A];
-      CSRArray[12'h180] = CSRArrayOld[12'h180];
       CSRArray[12'h140] = CSRArrayOld[12'h140];
-      CSRArray[12'h143] = CSRArrayOld[12'h143];
+      CSRArray[12'h141] = CSRArrayOld[12'h141];
       CSRArray[12'h142] = CSRArrayOld[12'h142];
+      CSRArray[12'h143] = CSRArrayOld[12'h143];
       CSRArray[12'h144] = CSRArrayOld[12'h144];
-      CSRArray[12'h14D] = CSRArrayOld[12'h14D];
-      // user CSRs
+
+      // Virtual Memory CSRs
+      CSRArray[12'h180] = CSRArrayOld[12'h180] ;
+
+      // Floating-Point CSRs
       CSRArray[12'h001] = CSRArrayOld[12'h001];
       CSRArray[12'h002] = CSRArrayOld[12'h002];
       CSRArray[12'h003] = CSRArrayOld[12'h003];
 
+      // Counters / Performance Monitoring CSRs
+      CSRArray[12'h306] = CSRArrayOld[12'h306];
+      CSRArray[12'h106] = CSRArrayOld[12'h106];
+      CSRArray[12'h320] = CSRArrayOld[12'h320];
+      // mhpmevent3-31 not connected (232-33F)
+      CSRArray[12'hB00] = CSRArrayOld[12'hB00];
+      CSRArray[12'hB02] = CSRArrayOld[12'hB02];
+      // mhpmcounter3-31 not connected (B03-B1F)
+      // cycle, time, instret not connected (C00-C02)
+      // hpmcounter3-31 not connected (C03-C1F)
+
+      // Machine Information Registers and Configuration CSRs
+      CSRArray[12'h301] = CSRArrayOld[12'h301];
+      CSRArray[12'h30A] = CSRArrayOld[12'h30A];
+      CSRArray[12'h10A] = CSRArrayOld[12'h10A];
+      CSRArray[12'h747] = CSRArrayOld[12'h747];
+      CSRArray[12'hF11] = CSRArrayOld[12'hF11];
+      CSRArray[12'hF12] = CSRArrayOld[12'hF12];
+      CSRArray[12'hF13] = CSRArrayOld[12'hF13];
+      CSRArray[12'hF14] = CSRArrayOld[12'hF14];
+      CSRArray[12'hF15] = CSRArrayOld[12'hF15];
+
+      // Sstc CSRs
+      CSRArray[12'h14D] = CSRArrayOld[12'h14D];
+      
+      // Zkr CSRs
+      // seed not connected (015)
+
+      // extra CSRs for RV32
       if (P.XLEN == 32) begin
         CSRArray[12'h310] = CSRArrayOld[12'h310];
         CSRArray[12'h31A] = CSRArrayOld[12'h31A];
+        CSRArray[12'h757] = CSRArrayOld[12'h757];
         CSRArray[12'h15D] = CSRArrayOld[12'h15D];
       end
     end    
@@ -345,194 +382,284 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   // record previous csr value.
   integer index4;
   always_ff @(posedge clk) begin
+    // PMP CFG 3A0 to 3AF
+    for(csrid='h3A0; csrid<='h3AF; csrid++)
+      CSRArrayOld[csrid] = CSRArray[csrid];
+    
+    // PMP ADDR 3B0 to 3EF
+    for(csrid='h3B0; csrid<='h3EF; csrid++)
+      CSRArrayOld[csrid] = CSRArray[csrid];
+
+    // M-mode trap CSRs
     CSRArrayOld[12'h300] = CSRArray[12'h300];
-    CSRArrayOld[12'h305] = CSRArray[12'h305];
-    CSRArrayOld[12'h341] = CSRArray[12'h341];
-    CSRArrayOld[12'h306] = CSRArray[12'h306];
-    CSRArrayOld[12'h320] = CSRArray[12'h320];
     CSRArrayOld[12'h302] = CSRArray[12'h302];
     CSRArrayOld[12'h303] = CSRArray[12'h303];
-    CSRArrayOld[12'h344] = CSRArray[12'h344];
     CSRArrayOld[12'h304] = CSRArray[12'h304];
-    CSRArrayOld[12'h301] = CSRArray[12'h301];
-    CSRArrayOld[12'h30A] = CSRArray[12'h30A];
-    CSRArrayOld[12'hF14] = CSRArray[12'hF14];
+    CSRArrayOld[12'h305] = CSRArray[12'h305];
     CSRArrayOld[12'h340] = CSRArray[12'h340];
+    CSRArrayOld[12'h341] = CSRArray[12'h341];
     CSRArrayOld[12'h342] = CSRArray[12'h342];
     CSRArrayOld[12'h343] = CSRArray[12'h343];
-    CSRArrayOld[12'hF11] = CSRArray[12'hF11];
-    CSRArrayOld[12'hF12] = CSRArray[12'hF12];
-    CSRArrayOld[12'hF13] = CSRArray[12'hF13];
-    CSRArrayOld[12'hF15] = CSRArray[12'hF15];
-    CSRArrayOld[12'h34A] = CSRArray[12'h34A];
-    // MCYCLE and MINSTRET
-    CSRArrayOld[12'hB00] = CSRArray[12'hB00];
-    CSRArrayOld[12'hB02] = CSRArray[12'hB02];
-    // supervisor CSRs
+    CSRArrayOld[12'h344] = CSRArray[12'h344];
+
+    // S-mode trap CSRs
     CSRArrayOld[12'h100] = CSRArray[12'h100];
     CSRArrayOld[12'h104] = CSRArray[12'h104];
     CSRArrayOld[12'h105] = CSRArray[12'h105];
-    CSRArrayOld[12'h141] = CSRArray[12'h141];
-    CSRArrayOld[12'h106] = CSRArray[12'h106];
-    CSRArrayOld[12'h10A] = CSRArray[12'h10A];
-    CSRArrayOld[12'h180] = CSRArray[12'h180];
     CSRArrayOld[12'h140] = CSRArray[12'h140];
-    CSRArrayOld[12'h143] = CSRArray[12'h143];
+    CSRArrayOld[12'h141] = CSRArray[12'h141];
     CSRArrayOld[12'h142] = CSRArray[12'h142];
+    CSRArrayOld[12'h143] = CSRArray[12'h143];
     CSRArrayOld[12'h144] = CSRArray[12'h144];
-    CSRArrayOld[12'h14D] = CSRArray[12'h14D];
-    // user CSRs
+
+    // Virtual Memory CSRs
+    CSRArrayOld[12'h180] = CSRArray[12'h180] ;
+
+    // Floating-Point CSRs
     CSRArrayOld[12'h001] = CSRArray[12'h001];
     CSRArrayOld[12'h002] = CSRArray[12'h002];
     CSRArrayOld[12'h003] = CSRArray[12'h003];
 
+    // Counters / Performance Monitoring CSRs
+    CSRArrayOld[12'h306] = CSRArray[12'h306];
+    CSRArrayOld[12'h106] = CSRArray[12'h106];
+    CSRArrayOld[12'h320] = CSRArray[12'h320];
+    // mhpmevent3-31 not connected (232-33F)
+    CSRArrayOld[12'hB00] = CSRArray[12'hB00];
+    CSRArrayOld[12'hB02] = CSRArray[12'hB02];
+    // mhpmcounter3-31 not connected (B03-B1F)
+    // cycle, time, instret not connected (C00-C02)
+    // hpmcounter3-31 not connected (C03-C1F)
+
+    // Machine Information Registers and Configuration CSRs
+    CSRArrayOld[12'h301] = CSRArray[12'h301];
+    CSRArrayOld[12'h30A] = CSRArray[12'h30A];
+    CSRArrayOld[12'h10A] = CSRArray[12'h10A];
+    CSRArrayOld[12'h747] = CSRArray[12'h747];
+    CSRArrayOld[12'hF11] = CSRArray[12'hF11];
+    CSRArrayOld[12'hF12] = CSRArray[12'hF12];
+    CSRArrayOld[12'hF13] = CSRArray[12'hF13];
+    CSRArrayOld[12'hF14] = CSRArray[12'hF14];
+    CSRArrayOld[12'hF15] = CSRArray[12'hF15];
+
+    // Sstc CSRs
+    CSRArrayOld[12'h14D] = CSRArray[12'h14D];
+    
+    // Zkr CSRs
+    // seed not connected (015)
+
+    // extra CSRs for RV32
     if (P.XLEN == 32) begin
       CSRArrayOld[12'h310] = CSRArray[12'h310];
       CSRArrayOld[12'h31A] = CSRArray[12'h31A];
+      CSRArrayOld[12'h757] = CSRArray[12'h757];
       CSRArrayOld[12'h15D] = CSRArray[12'h15D];
     end
-    
-    // PMP CFG 3A0 to 3AF
-    for(index4='h3A0; index4<='h3AF; index4++)
-        CSRArrayOld[index4] = CSRArray[index4];
-    
-    // PMP ADDR 3B0 to 3EF
-    for(index4='h3B0; index4<='h3EF; index4++)
-        CSRArrayOld[index4] = CSRArray[index4];
   end
   
   // check for csr value change.
+  // M-mode trap CSRs
   assign CSR_W[12'h300] = (CSRArrayOld[12'h300] != CSRArray[12'h300]) ? 1 : 0;
-  assign CSR_W[12'h305] = (CSRArrayOld[12'h305] != CSRArray[12'h305]) ? 1 : 0;
-  assign CSR_W[12'h341] = (CSRArrayOld[12'h341] != CSRArray[12'h341]) ? 1 : 0;
-  assign CSR_W[12'h306] = (CSRArrayOld[12'h306] != CSRArray[12'h306]) ? 1 : 0;
-  assign CSR_W[12'h30A] = (CSRArrayOld[12'h30A] != CSRArray[12'h30A]) ? 1 : 0;
-  assign CSR_W[12'h320] = (CSRArrayOld[12'h320] != CSRArray[12'h320]) ? 1 : 0;
   assign CSR_W[12'h302] = (CSRArrayOld[12'h302] != CSRArray[12'h302]) ? 1 : 0;
   assign CSR_W[12'h303] = (CSRArrayOld[12'h303] != CSRArray[12'h303]) ? 1 : 0;
-  assign CSR_W[12'h344] = (CSRArrayOld[12'h344] != CSRArray[12'h344]) ? 1 : 0;
   assign CSR_W[12'h304] = (CSRArrayOld[12'h304] != CSRArray[12'h304]) ? 1 : 0;
-  assign CSR_W[12'h301] = (CSRArrayOld[12'h301] != CSRArray[12'h301]) ? 1 : 0;
-  assign CSR_W[12'hF14] = (CSRArrayOld[12'hF14] != CSRArray[12'hF14]) ? 1 : 0;
+  assign CSR_W[12'h305] = (CSRArrayOld[12'h305] != CSRArray[12'h305]) ? 1 : 0;
   assign CSR_W[12'h340] = (CSRArrayOld[12'h340] != CSRArray[12'h340]) ? 1 : 0;
+  assign CSR_W[12'h341] = (CSRArrayOld[12'h341] != CSRArray[12'h341]) ? 1 : 0;
   assign CSR_W[12'h342] = (CSRArrayOld[12'h342] != CSRArray[12'h342]) ? 1 : 0;
   assign CSR_W[12'h343] = (CSRArrayOld[12'h343] != CSRArray[12'h343]) ? 1 : 0;
-  assign CSR_W[12'hF11] = (CSRArrayOld[12'hF11] != CSRArray[12'hF11]) ? 1 : 0;
-  assign CSR_W[12'hF12] = (CSRArrayOld[12'hF12] != CSRArray[12'hF12]) ? 1 : 0;
-  assign CSR_W[12'hF13] = (CSRArrayOld[12'hF13] != CSRArray[12'hF13]) ? 1 : 0;
-  assign CSR_W[12'hF15] = (CSRArrayOld[12'hF15] != CSRArray[12'hF15]) ? 1 : 0;
-  assign CSR_W[12'h34A] = (CSRArrayOld[12'h34A] != CSRArray[12'h34A]) ? 1 : 0;
-  assign CSR_W[12'hB00] = (CSRArrayOld[12'hB00] != CSRArray[12'hB00]) ? 1 : 0;
-  assign CSR_W[12'hB02] = (CSRArrayOld[12'hB02] != CSRArray[12'hB02]) ? 1 : 0;
+  assign CSR_W[12'h344] = (CSRArrayOld[12'h344] != CSRArray[12'h344]) ? 1 : 0;
+
+  // S-mode trap CSRs
   assign CSR_W[12'h100] = (CSRArrayOld[12'h100] != CSRArray[12'h100]) ? 1 : 0;
   assign CSR_W[12'h104] = (CSRArrayOld[12'h104] != CSRArray[12'h104]) ? 1 : 0;
   assign CSR_W[12'h105] = (CSRArrayOld[12'h105] != CSRArray[12'h105]) ? 1 : 0;
-  assign CSR_W[12'h141] = (CSRArrayOld[12'h141] != CSRArray[12'h141]) ? 1 : 0;
-  assign CSR_W[12'h106] = (CSRArrayOld[12'h106] != CSRArray[12'h106]) ? 1 : 0;
-  assign CSR_W[12'h10A] = (CSRArrayOld[12'h10A] != CSRArray[12'h10A]) ? 1 : 0;
-  assign CSR_W[12'h180] = (CSRArrayOld[12'h180] != CSRArray[12'h180]) ? 1 : 0;
   assign CSR_W[12'h140] = (CSRArrayOld[12'h140] != CSRArray[12'h140]) ? 1 : 0;
-  assign CSR_W[12'h143] = (CSRArrayOld[12'h143] != CSRArray[12'h143]) ? 1 : 0;
+  assign CSR_W[12'h141] = (CSRArrayOld[12'h141] != CSRArray[12'h141]) ? 1 : 0;
   assign CSR_W[12'h142] = (CSRArrayOld[12'h142] != CSRArray[12'h142]) ? 1 : 0;
+  assign CSR_W[12'h143] = (CSRArrayOld[12'h143] != CSRArray[12'h143]) ? 1 : 0;
   assign CSR_W[12'h144] = (CSRArrayOld[12'h144] != CSRArray[12'h144]) ? 1 : 0;
-  assign CSR_W[12'h14D] = (CSRArrayOld[12'h14D] != CSRArray[12'h14D]) ? 1 : 0;
+
+  // Virtual Memory CSRs
+  assign CSR_W[12'h180] = (CSRArrayOld[12'h180] != CSRArray[12'h180]) ? 1 : 0;
+
+  // Floating-Point CSRs
   assign CSR_W[12'h001] = (CSRArrayOld[12'h001] != CSRArray[12'h001]) ? 1 : 0;
   assign CSR_W[12'h002] = (CSRArrayOld[12'h002] != CSRArray[12'h002]) ? 1 : 0;
   assign CSR_W[12'h003] = (CSRArrayOld[12'h003] != CSRArray[12'h003]) ? 1 : 0;
 
+  // Counters / Performance Monitoring CSRs
+  assign CSR_W[12'h306] = (CSRArrayOld[12'h306] != CSRArray[12'h306]) ? 1 : 0;
+  assign CSR_W[12'h106] = (CSRArrayOld[12'h106] != CSRArray[12'h106]) ? 1 : 0;
+  assign CSR_W[12'h320] = (CSRArrayOld[12'h320] != CSRArray[12'h320]) ? 1 : 0;
+  // mhpmevent3-31 not connected (232-33F)
+  assign CSR_W[12'hB00] = (CSRArrayOld[12'hB00] != CSRArray[12'hB00]) ? 1 : 0;
+  assign CSR_W[12'hB02] = (CSRArrayOld[12'hB02] != CSRArray[12'hB02]) ? 1 : 0;
+  // mhpmcounter3-31 not connected (B03-B1F)
+  // cycle, time, instret not connected (C00-C02)
+  // hpmcounter3-31 not connected (C03-C1F)
+
+  // Machine Information Registers and Configuration CSRs
+  assign CSR_W[12'h301] = (CSRArrayOld[12'h301] != CSRArray[12'h301]) ? 1 : 0;
+  assign CSR_W[12'h30A] = (CSRArrayOld[12'h30A] != CSRArray[12'h30A]) ? 1 : 0;
+  assign CSR_W[12'h10A] = (CSRArrayOld[12'h10A] != CSRArray[12'h10A]) ? 1 : 0;
+  assign CSR_W[12'h747] = (CSRArrayOld[12'h747] != CSRArray[12'h747]) ? 1 : 0;
+  assign CSR_W[12'hF11] = (CSRArrayOld[12'hF11] != CSRArray[12'hF11]) ? 1 : 0;
+  assign CSR_W[12'hF12] = (CSRArrayOld[12'hF12] != CSRArray[12'hF12]) ? 1 : 0;
+  assign CSR_W[12'hF13] = (CSRArrayOld[12'hF13] != CSRArray[12'hF13]) ? 1 : 0;
+  assign CSR_W[12'hF14] = (CSRArrayOld[12'hF14] != CSRArray[12'hF14]) ? 1 : 0;
+  assign CSR_W[12'hF15] = (CSRArrayOld[12'hF15] != CSRArray[12'hF15]) ? 1 : 0;
+
+  // Sstc CSRs
+  assign CSR_W[12'h14D] = (CSRArrayOld[12'h14D] != CSRArray[12'h14D]) ? 1 : 0;
+  
+  // Zkr CSRs
+  // seed not connected (015)
+
+  // extra CSRs for RV32
   if (P.XLEN == 32) begin
     assign CSR_W[12'h310] = (CSRArrayOld[12'h310] != CSRArray[12'h310]) ? 1 : 0;
     assign CSR_W[12'h31A] = (CSRArrayOld[12'h31A] != CSRArray[12'h31A]) ? 1 : 0;
+    assign CSR_W[12'h757] = (CSRArrayOld[12'h757] != CSRArray[12'h757]) ? 1 : 0;
     assign CSR_W[12'h15D] = (CSRArrayOld[12'h15D] != CSRArray[12'h15D]) ? 1 : 0;
   end
-  
+
+
+  // M-mode trap CSRs
   assign rvvi.csr_wb[0][0][12'h300] = CSR_W[12'h300];
-  assign rvvi.csr_wb[0][0][12'h305] = CSR_W[12'h305];
-  assign rvvi.csr_wb[0][0][12'h341] = CSR_W[12'h341];
-  assign rvvi.csr_wb[0][0][12'h306] = CSR_W[12'h306];
-  assign rvvi.csr_wb[0][0][12'h320] = CSR_W[12'h320];
   assign rvvi.csr_wb[0][0][12'h302] = CSR_W[12'h302];
   assign rvvi.csr_wb[0][0][12'h303] = CSR_W[12'h303];
-  assign rvvi.csr_wb[0][0][12'h344] = CSR_W[12'h344];
   assign rvvi.csr_wb[0][0][12'h304] = CSR_W[12'h304];
-  assign rvvi.csr_wb[0][0][12'h30A] = CSR_W[12'h30A];
-  assign rvvi.csr_wb[0][0][12'h301] = CSR_W[12'h301];
-  assign rvvi.csr_wb[0][0][12'hF14] = CSR_W[12'hF14];
+  assign rvvi.csr_wb[0][0][12'h305] = CSR_W[12'h305];
   assign rvvi.csr_wb[0][0][12'h340] = CSR_W[12'h340];
+  assign rvvi.csr_wb[0][0][12'h341] = CSR_W[12'h341];
   assign rvvi.csr_wb[0][0][12'h342] = CSR_W[12'h342];
   assign rvvi.csr_wb[0][0][12'h343] = CSR_W[12'h343];
-  assign rvvi.csr_wb[0][0][12'hF11] = CSR_W[12'hF11];
-  assign rvvi.csr_wb[0][0][12'hF12] = CSR_W[12'hF12];
-  assign rvvi.csr_wb[0][0][12'hF13] = CSR_W[12'hF13];
-  assign rvvi.csr_wb[0][0][12'hF15] = CSR_W[12'hF15];
-  assign rvvi.csr_wb[0][0][12'h34A] = CSR_W[12'h34A];
-  assign rvvi.csr_wb[0][0][12'hB00] = CSR_W[12'hB00];
-  assign rvvi.csr_wb[0][0][12'hB02] = CSR_W[12'hB02];
+  assign rvvi.csr_wb[0][0][12'h344] = CSR_W[12'h344];
+
+  // S-mode trap CSRs
   assign rvvi.csr_wb[0][0][12'h100] = CSR_W[12'h100];
   assign rvvi.csr_wb[0][0][12'h104] = CSR_W[12'h104];
   assign rvvi.csr_wb[0][0][12'h105] = CSR_W[12'h105];
-  assign rvvi.csr_wb[0][0][12'h141] = CSR_W[12'h141];
-  assign rvvi.csr_wb[0][0][12'h106] = CSR_W[12'h106];
-  assign rvvi.csr_wb[0][0][12'h10A] = CSR_W[12'h10A];
-  assign rvvi.csr_wb[0][0][12'h180] = CSR_W[12'h180];
   assign rvvi.csr_wb[0][0][12'h140] = CSR_W[12'h140];
-  assign rvvi.csr_wb[0][0][12'h143] = CSR_W[12'h143];
+  assign rvvi.csr_wb[0][0][12'h141] = CSR_W[12'h141];
   assign rvvi.csr_wb[0][0][12'h142] = CSR_W[12'h142];
+  assign rvvi.csr_wb[0][0][12'h143] = CSR_W[12'h143];
   assign rvvi.csr_wb[0][0][12'h144] = CSR_W[12'h144];
-  assign rvvi.csr_wb[0][0][12'h14D] = CSR_W[12'h14D];
+
+  // Virtual Memory CSRs
+  assign rvvi.csr_wb[0][0][12'h180] = CSR_W[12'h180];
+
+  // Floating-Point CSRs
   assign rvvi.csr_wb[0][0][12'h001] = CSR_W[12'h001];
   assign rvvi.csr_wb[0][0][12'h002] = CSR_W[12'h002];
   assign rvvi.csr_wb[0][0][12'h003] = CSR_W[12'h003];
 
+  // Counters / Performance Monitoring CSRs
+  assign rvvi.csr_wb[0][0][12'h306] = CSR_W[12'h306];
+  assign rvvi.csr_wb[0][0][12'h106] = CSR_W[12'h106];
+  assign rvvi.csr_wb[0][0][12'h320] = CSR_W[12'h320];
+  // mhpmevent3-31 not connected (232-33F)
+  assign rvvi.csr_wb[0][0][12'hB00] = CSR_W[12'hB00];
+  assign rvvi.csr_wb[0][0][12'hB02] = CSR_W[12'hB02];
+  // mhpmcounter3-31 not connected (B03-B1F)
+  // cycle, time, instret not connected (C00-C02)
+  // hpmcounter3-31 not connected (C03-C1F)
+
+  // Machine Information Registers and Configuration CSRs
+  assign rvvi.csr_wb[0][0][12'h301] = CSR_W[12'h301];
+  assign rvvi.csr_wb[0][0][12'h30A] = CSR_W[12'h30A];
+  assign rvvi.csr_wb[0][0][12'h10A] = CSR_W[12'h10A];
+  assign rvvi.csr_wb[0][0][12'h747] = CSR_W[12'h747];
+  assign rvvi.csr_wb[0][0][12'hF11] = CSR_W[12'hF11];
+  assign rvvi.csr_wb[0][0][12'hF12] = CSR_W[12'hF12];
+  assign rvvi.csr_wb[0][0][12'hF13] = CSR_W[12'hF13];
+  assign rvvi.csr_wb[0][0][12'hF14] = CSR_W[12'hF14];
+  assign rvvi.csr_wb[0][0][12'hF15] = CSR_W[12'hF15];
+
+  // Sstc CSRs
+  assign rvvi.csr_wb[0][0][12'h14D] = CSR_W[12'h14D];
+  
+  // Zkr CSRs
+  // seed not connected (015)
+
+  // extra CSRs for RV32
   if (P.XLEN == 32) begin
     assign rvvi.csr_wb[0][0][12'h310] = CSR_W[12'h310];
     assign rvvi.csr_wb[0][0][12'h31A] = CSR_W[12'h31A];
+    assign rvvi.csr_wb[0][0][12'h757] = CSR_W[12'h757];
     assign rvvi.csr_wb[0][0][12'h15D] = CSR_W[12'h15D];
   end
 
-  assign rvvi.csr[0][0][12'h300]    = CSRArray[12'h300];
-  assign rvvi.csr[0][0][12'h305]    = CSRArray[12'h305];
-  assign rvvi.csr[0][0][12'h341]    = CSRArray[12'h341];
-  assign rvvi.csr[0][0][12'h306]    = CSRArray[12'h306];
-  assign rvvi.csr[0][0][12'h320]    = CSRArray[12'h320];
-  assign rvvi.csr[0][0][12'h302]    = CSRArray[12'h302];
-  assign rvvi.csr[0][0][12'h303]    = CSRArray[12'h303];
-  assign rvvi.csr[0][0][12'h344]    = CSRArray[12'h344];
-  assign rvvi.csr[0][0][12'h304]    = CSRArray[12'h304];
-  assign rvvi.csr[0][0][12'h30A]    = CSRArray[12'h30A];
-  assign rvvi.csr[0][0][12'h301]    = CSRArray[12'h301];
-  assign rvvi.csr[0][0][12'hF14]    = CSRArray[12'hF14];
-  assign rvvi.csr[0][0][12'h340]    = CSRArray[12'h340];
-  assign rvvi.csr[0][0][12'h342]    = CSRArray[12'h342];
-  assign rvvi.csr[0][0][12'h343]    = CSRArray[12'h343];
-  assign rvvi.csr[0][0][12'hF11]    = CSRArray[12'hF11];
-  assign rvvi.csr[0][0][12'hF12]    = CSRArray[12'hF12];
-  assign rvvi.csr[0][0][12'hF13]    = CSRArray[12'hF13];
-  assign rvvi.csr[0][0][12'hF15]    = CSRArray[12'hF15];
-  assign rvvi.csr[0][0][12'h34A]    = CSRArray[12'h34A];
-  assign rvvi.csr[0][0][12'hB00]    = CSRArray[12'hB00];
-  assign rvvi.csr[0][0][12'hB02]    = CSRArray[12'hB02];
-  assign rvvi.csr[0][0][12'h100]    = CSRArray[12'h100];
-  assign rvvi.csr[0][0][12'h104]    = CSRArray[12'h104];
-  assign rvvi.csr[0][0][12'h105]    = CSRArray[12'h105];
-  assign rvvi.csr[0][0][12'h141]    = CSRArray[12'h141];
-  assign rvvi.csr[0][0][12'h106]    = CSRArray[12'h106];
-  assign rvvi.csr[0][0][12'h10A]    = CSRArray[12'h10A];
-  assign rvvi.csr[0][0][12'h180]    = CSRArray[12'h180];
-  assign rvvi.csr[0][0][12'h140]    = CSRArray[12'h140];
-  assign rvvi.csr[0][0][12'h143]    = CSRArray[12'h143];
-  assign rvvi.csr[0][0][12'h142]    = CSRArray[12'h142];
-  assign rvvi.csr[0][0][12'h144]    = CSRArray[12'h144];
-  assign rvvi.csr[0][0][12'h14D]    = CSRArray[12'h14D];
-  assign rvvi.csr[0][0][12'h001]    = CSRArray[12'h001];
-  assign rvvi.csr[0][0][12'h002]    = CSRArray[12'h002];
-  assign rvvi.csr[0][0][12'h003]    = CSRArray[12'h003];
 
+
+
+// M-mode trap CSRs
+  assign rvvi.csr[0][0][12'h300] = CSRArray[12'h300];
+  assign rvvi.csr[0][0][12'h302] = CSRArray[12'h302];
+  assign rvvi.csr[0][0][12'h303] = CSRArray[12'h303];
+  assign rvvi.csr[0][0][12'h304] = CSRArray[12'h304];
+  assign rvvi.csr[0][0][12'h305] = CSRArray[12'h305];
+  assign rvvi.csr[0][0][12'h340] = CSRArray[12'h340];
+  assign rvvi.csr[0][0][12'h341] = CSRArray[12'h341];
+  assign rvvi.csr[0][0][12'h342] = CSRArray[12'h342];
+  assign rvvi.csr[0][0][12'h343] = CSRArray[12'h343];
+  assign rvvi.csr[0][0][12'h344] = CSRArray[12'h344];
+
+  // S-mode trap CSRs
+  assign rvvi.csr[0][0][12'h100] = CSRArray[12'h100];
+  assign rvvi.csr[0][0][12'h104] = CSRArray[12'h104];
+  assign rvvi.csr[0][0][12'h105] = CSRArray[12'h105];
+  assign rvvi.csr[0][0][12'h140] = CSRArray[12'h140];
+  assign rvvi.csr[0][0][12'h141] = CSRArray[12'h141];
+  assign rvvi.csr[0][0][12'h142] = CSRArray[12'h142];
+  assign rvvi.csr[0][0][12'h143] = CSRArray[12'h143];
+  assign rvvi.csr[0][0][12'h144] = CSRArray[12'h144];
+
+  // Virtual Memory CSRs
+  assign rvvi.csr[0][0][12'h180] = CSRArray[12'h180];
+
+  // Floating-Point CSRs
+  assign rvvi.csr[0][0][12'h001] = CSRArray[12'h001];
+  assign rvvi.csr[0][0][12'h002] = CSRArray[12'h002];
+  assign rvvi.csr[0][0][12'h003] = CSRArray[12'h003];
+
+  // Counters / Performance Monitoring CSRs
+  assign rvvi.csr[0][0][12'h306] = CSRArray[12'h306];
+  assign rvvi.csr[0][0][12'h106] = CSRArray[12'h106];
+  assign rvvi.csr[0][0][12'h320] = CSRArray[12'h320];
+  // mhpmevent3-31 not connected (232-33F)
+  assign rvvi.csr[0][0][12'hB00] = CSRArray[12'hB00];
+  assign rvvi.csr[0][0][12'hB02] = CSRArray[12'hB02];
+  // mhpmcounter3-31 not connected (B03-B1F)
+  // cycle, time, instret not connected (C00-C02)
+  // hpmcounter3-31 not connected (C03-C1F)
+
+  // Machine Information Registers and Configuration CSRs
+  assign rvvi.csr[0][0][12'h301] = CSRArray[12'h301];
+  assign rvvi.csr[0][0][12'h30A] = CSRArray[12'h30A];
+  assign rvvi.csr[0][0][12'h10A] = CSRArray[12'h10A];
+  assign rvvi.csr[0][0][12'h747] = CSRArray[12'h747];
+  assign rvvi.csr[0][0][12'hF11] = CSRArray[12'hF11];
+  assign rvvi.csr[0][0][12'hF12] = CSRArray[12'hF12];
+  assign rvvi.csr[0][0][12'hF13] = CSRArray[12'hF13];
+  assign rvvi.csr[0][0][12'hF14] = CSRArray[12'hF14];
+  assign rvvi.csr[0][0][12'hF15] = CSRArray[12'hF15];
+
+  // Sstc CSRs
+  assign rvvi.csr[0][0][12'h14D] = CSRArray[12'h14D];
+  
+  // Zkr CSRs
+  // seed not connected (015)
+
+  // extra CSRs for RV32
   if (P.XLEN == 32) begin
     assign rvvi.csr[0][0][12'h310] = CSRArray[12'h310];
     assign rvvi.csr[0][0][12'h31A] = CSRArray[12'h31A];
+    assign rvvi.csr[0][0][12'h757] = CSRArray[12'h757];
     assign rvvi.csr[0][0][12'h15D] = CSRArray[12'h15D];
   end
+
   
   // PMP CFG 3A0 to 3AF
   for(index='h3A0; index<='h3AF; index++) begin