Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Move InstrPageFault to fetch stage

Browse Source
This commit is contained in:
Thomas Fleming 2021-04-13 13:39:22 -04:00
parent dc8a165806
commit 6188f10732
3 changed files with 23 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
wally-pipelined/src/ebu/pagetablewalker.sv
View File

@ -61,7 +61,7 @@ module pagetablewalker (
output logic MMUTranslationComplete, output logic MMUTranslationComplete,
// Faults // Faults
output logic InstrPageFaultM, LoadPageFaultM, StorePageFaultM output logic InstrPageFaultF, LoadPageFaultM, StorePageFaultM
); );
// Internal signals // Internal signals
@ -154,7 +154,8 @@ module pagetablewalker (
// else if (~ValidPTE || (LeafPTE && BadMegapage)) // else if (~ValidPTE || (LeafPTE && BadMegapage))
// NextWalkerState = FAULT; // NextWalkerState = FAULT;
// *** Leave megapage implementation for later // *** Leave megapage implementation for later
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** need to check if megapage valid/aligned
else if (ValidPTE && LeafPTE) NextWalkerState = LEAF;
else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL0; else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL0;
else NextWalkerState = FAULT; else NextWalkerState = FAULT;
LEVEL0: if (~MMUReady) NextWalkerState = LEVEL0; LEVEL0: if (~MMUReady) NextWalkerState = LEVEL0;
@ -185,7 +186,7 @@ module pagetablewalker (
assign MMUTranslationComplete = '0; assign MMUTranslationComplete = '0;
assign DTLBWriteM = '0; assign DTLBWriteM = '0;
assign ITLBWriteF = '0; assign ITLBWriteF = '0;
assign InstrPageFaultM = '0; assign InstrPageFaultF = '0;
assign LoadPageFaultM = '0; assign LoadPageFaultM = '0;
assign StorePageFaultM = '0; assign StorePageFaultM = '0;
@ -208,7 +209,7 @@ module pagetablewalker (
FAULT: begin FAULT: begin
assign TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; assign TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
assign MMUTranslationComplete = '1; assign MMUTranslationComplete = '1;
assign InstrPageFaultM = ~DTLBMissM; assign InstrPageFaultF = ~DTLBMissM;
assign LoadPageFaultM = DTLBMissM && ~MemStore; assign LoadPageFaultM = DTLBMissM && ~MemStore;
assign StorePageFaultM = DTLBMissM && MemStore; assign StorePageFaultM = DTLBMissM && MemStore;
end end
@ -243,13 +244,14 @@ module pagetablewalker (
IDLE: if (MMUTranslate) NextWalkerState = LEVEL2; IDLE: if (MMUTranslate) NextWalkerState = LEVEL2;
else NextWalkerState = IDLE; else NextWalkerState = IDLE;
LEVEL2: if (~MMUReady) NextWalkerState = LEVEL2; LEVEL2: if (~MMUReady) NextWalkerState = LEVEL2;
else if (ValidPTE && LeafPTE) NextWalkerState = LEAF;
else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL1; else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL1;
else NextWalkerState = FAULT; else NextWalkerState = FAULT;
LEVEL1: if (~MMUReady) NextWalkerState = LEVEL1; LEVEL1: if (~MMUReady) NextWalkerState = LEVEL1;
// else if (~ValidPTE || (LeafPTE && BadMegapage)) // else if (~ValidPTE || (LeafPTE && BadMegapage))
// NextWalkerState = FAULT; // NextWalkerState = FAULT;
// *** Leave megapage implementation for later // *** Leave megapage implementation for later
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; else if (ValidPTE && LeafPTE) NextWalkerState = LEAF;
else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL0; else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL0;
else NextWalkerState = FAULT; else NextWalkerState = FAULT;
LEVEL0: if (~MMUReady) NextWalkerState = LEVEL0; LEVEL0: if (~MMUReady) NextWalkerState = LEVEL0;
@ -285,7 +287,7 @@ module pagetablewalker (
assign MMUTranslationComplete = '0; assign MMUTranslationComplete = '0;
assign DTLBWriteM = '0; assign DTLBWriteM = '0;
assign ITLBWriteF = '0; assign ITLBWriteF = '0;
assign InstrPageFaultM = '0; assign InstrPageFaultF = '0;
assign LoadPageFaultM = '0; assign LoadPageFaultM = '0;
assign StorePageFaultM = '0; assign StorePageFaultM = '0;
@ -312,7 +314,7 @@ module pagetablewalker (
FAULT: begin FAULT: begin
assign TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; assign TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
assign MMUTranslationComplete = '1; assign MMUTranslationComplete = '1;
assign InstrPageFaultM = ~DTLBMissM; assign InstrPageFaultF = ~DTLBMissM;
assign LoadPageFaultM = DTLBMissM && ~MemStore; assign LoadPageFaultM = DTLBMissM && ~MemStore;
assign StorePageFaultM = DTLBMissM && MemStore; assign StorePageFaultM = DTLBMissM && MemStore;
end end

19
wally-pipelined/src/privileged/privileged.sv
View File

@ -40,7 +40,7 @@ module privileged (
input logic InstrValidW, FloatRegWriteW, LoadStallD, BPPredWrongM, input logic InstrValidW, FloatRegWriteW, LoadStallD, BPPredWrongM,
input logic [3:0] InstrClassM, input logic [3:0] InstrClassM,
input logic PrivilegedM, input logic PrivilegedM,
input logic InstrPageFaultM, LoadPageFaultM, StorePageFaultM, input logic InstrPageFaultF, LoadPageFaultM, StorePageFaultM,
input logic InstrMisalignedFaultM, InstrAccessFaultF, IllegalIEUInstrFaultD, input logic InstrMisalignedFaultM, InstrAccessFaultF, IllegalIEUInstrFaultD,
input logic LoadMisalignedFaultM, LoadAccessFaultM, input logic LoadMisalignedFaultM, LoadAccessFaultM,
input logic StoreMisalignedFaultM, StoreAccessFaultM, input logic StoreMisalignedFaultM, StoreAccessFaultM,
@ -63,6 +63,7 @@ module privileged (
logic uretM, sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM; logic uretM, sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM;
logic IllegalCSRAccessM; logic IllegalCSRAccessM;
logic IllegalIEUInstrFaultE, IllegalIEUInstrFaultM; logic IllegalIEUInstrFaultE, IllegalIEUInstrFaultM;
logic InstrPageFaultD, InstrPageFaultE, InstrPageFaultM;
logic InstrAccessFaultD, InstrAccessFaultE, InstrAccessFaultM; logic InstrAccessFaultD, InstrAccessFaultE, InstrAccessFaultM;
logic IllegalInstrFaultM; logic IllegalInstrFaultM;
@ -129,13 +130,15 @@ module privileged (
// assign StorePageFaultM = 0; // assign StorePageFaultM = 0;
// pipeline fault signals // pipeline fault signals
flopenrc #(1) faultregD(clk, reset, FlushD, ~StallD, InstrAccessFaultF, InstrAccessFaultD); flopenrc #(2) faultregD(clk, reset, FlushD, ~StallD,
flopenrc #(2) faultregE(clk, reset, FlushE, ~StallE, {InstrPageFaultF, InstrAccessFaultF},
{IllegalIEUInstrFaultD, InstrAccessFaultD}, // ** vs IllegalInstrFaultInD {InstrPageFaultD, InstrAccessFaultD});
{IllegalIEUInstrFaultE, InstrAccessFaultE}); flopenrc #(3) faultregE(clk, reset, FlushE, ~StallE,
flopenrc #(2) faultregM(clk, reset, FlushM, ~StallM, {IllegalIEUInstrFaultD, InstrPageFaultD, InstrAccessFaultD}, // ** vs IllegalInstrFaultInD
{IllegalIEUInstrFaultE, InstrAccessFaultE}, {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE});
{IllegalIEUInstrFaultM, InstrAccessFaultM}); flopenrc #(3) faultregM(clk, reset, FlushM, ~StallM,
{IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE},
{IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM});
trap trap(.*); trap trap(.*);

2
wally-pipelined/src/wally/wallypipelinedhart.sv
View File

@ -76,7 +76,7 @@ module wallypipelinedhart (
logic InstrMisalignedFaultM; logic InstrMisalignedFaultM;
logic DataMisalignedM; logic DataMisalignedM;
logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD; logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD;
logic InstrPageFaultM, LoadPageFaultM, StorePageFaultM; logic InstrPageFaultF, LoadPageFaultM, StorePageFaultM;
logic LoadMisalignedFaultM, LoadAccessFaultM; logic LoadMisalignedFaultM, LoadAccessFaultM;
logic StoreMisalignedFaultM, StoreAccessFaultM; logic StoreMisalignedFaultM, StoreAccessFaultM;
logic [`XLEN-1:0] InstrMisalignedAdrM; logic [`XLEN-1:0] InstrMisalignedAdrM;