From 3c848cd16c98fb5b4df1b9eae3cb173e9c5681ea Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 3 Dec 2024 09:56:03 -0600 Subject: [PATCH] Fixed bug in the wally tracer to support hptw pte accesses. --- testbench/common/wallyTracer.sv | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 51f0d302a..c873d5819 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -44,6 +44,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); logic [31:0] InstrRawD, InstrRawE, InstrRawM, InstrRawW; logic InstrValidM, InstrValidW; logic StallE, StallM, StallW; + logic GatedStallW; logic FlushD, FlushE, FlushM, FlushW; logic TrapM, TrapW; logic HaltM, HaltW; @@ -89,6 +90,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign StallE = testbench.dut.core.StallE; assign StallM = testbench.dut.core.StallM; assign StallW = testbench.dut.core.StallW; + assign GatedStallW = testbench.dut.core.lsu.GatedStallW; assign FlushD = testbench.dut.core.FlushD; assign FlushE = testbench.dut.core.FlushE; assign FlushM = testbench.dut.core.FlushM; @@ -359,12 +361,12 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); flopenrc #(P.XLEN) VAdrDWReg (clk, reset, FlushW, ~StallW, VAdrDM, VAdrDW); flopenrc #(P.PA_BITS) PAIWReg (clk, reset, FlushW, ~StallW, PAIM, PAIW); flopenrc #(P.PA_BITS) PADWReg (clk, reset, FlushW, ~StallW, PADM, PADW); - flopenrc #(P.XLEN) PTE_iWReg (clk, reset, FlushW, ~StallW, PTE_iM, PTE_iW); - flopenrc #(P.XLEN) PTE_dWReg (clk, reset, FlushW, ~StallW, PTE_dM, PTE_dW); - flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, FlushW, ~StallW, PPN_iM, PPN_iW); - flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~StallW, PPN_dM, PPN_dW); - flopenrc #(1) ReadAccessWReg (clk, reset, FlushW, ~StallW, ReadAccessM, ReadAccessW); - flopenrc #(1) WriteAccessWReg (clk, reset, FlushW, ~StallW, WriteAccessM, WriteAccessW); + flopenrc #(P.XLEN) PTE_iWReg (clk, reset, FlushW, ~GatedStallW, PTE_iM, PTE_iW); + flopenrc #(P.XLEN) PTE_dWReg (clk, reset, FlushW, ~GatedStallW, PTE_dM, PTE_dW); + flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, FlushW, ~GatedStallW, PPN_iM, PPN_iW); + flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~GatedStallW, PPN_dM, PPN_dW); + flopenrc #(1) ReadAccessWReg (clk, reset, FlushW, ~GatedStallW, ReadAccessM, ReadAccessW); + flopenrc #(1) WriteAccessWReg (clk, reset, FlushW, ~GatedStallW, WriteAccessM, WriteAccessW); // *** what is this used for? flopenrc #(1) ExecuteAccessDReg (clk, reset, FlushE, ~StallE, ExecuteAccessF, ExecuteAccessD); flopenrc #(1) ExecuteAccessEReg (clk, reset, FlushE, ~StallE, ExecuteAccessD, ExecuteAccessE);