mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Finally have the ptw correctly walking through the dcache to update the itlb.
Still not working fully.
This commit is contained in:
Ross Thompson
parent
d41c9d5ad9
commit
6163629204
@ -3,48 +3,49 @@ quietly WaveActivateNextPane {} 0
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add wave -noupdate /testbench/clk
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add wave -noupdate /testbench/clk
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add wave -noupdate /testbench/reset
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add wave -noupdate /testbench/reset
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add wave -noupdate /testbench/memfilename
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add wave -noupdate /testbench/memfilename
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add wave -noupdate /testbench/dut/hart/SATP_REGW
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add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
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add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM
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add wave -noupdate -group {Memory Stage} /testbench/dut/hart/PCM
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add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
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add wave -noupdate -group {Memory Stage} /testbench/InstrMName
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
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add wave -noupdate -group {Memory Stage} /testbench/dut/hart/InstrM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
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add wave -noupdate -group HDU -expand -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
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add wave -noupdate -group HDU -expand -group interrupts /testbench/dut/hart/priv/trap/CommittedM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -group HDU -expand -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
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add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
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add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
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@ -112,7 +113,7 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
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add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rf
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
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@ -155,12 +156,12 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/Write
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
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add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF
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add wave -noupdate -group PCS /testbench/dut/hart/PCF
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add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD
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add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD
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add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE
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add wave -noupdate -group PCS /testbench/dut/hart/PCE
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add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM
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add wave -noupdate -group PCS /testbench/dut/hart/PCM
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add wave -noupdate -expand -group PCS /testbench/PCW
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add wave -noupdate -group PCS /testbench/PCW
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/InstrD
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/InstrD
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcAE
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcAE
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcBE
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcBE
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@ -239,6 +240,12 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrE
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/HPTWPAdrE
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/HPTWPAdrM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrMtoDCache
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrEtoDCache
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add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/CurrState
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add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/CurrState
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
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@ -271,18 +278,23 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cach
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
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add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty
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add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid
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add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM
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add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM
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add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW
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||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
|
||||||
@ -297,6 +309,9 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memo
|
|||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrM
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrM
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrOffsetM
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrMaskedM
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Cacheable
|
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Cacheable
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Idempotent
|
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Idempotent
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/AtomicAllowed
|
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/AtomicAllowed
|
||||||
@ -306,6 +321,10 @@ add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PM
|
|||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/SVMode
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
|
||||||
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss
|
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss
|
||||||
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit
|
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit
|
||||||
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress
|
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress
|
||||||
@ -351,26 +370,28 @@ add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME
|
|||||||
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP
|
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP
|
||||||
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM
|
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM
|
||||||
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM
|
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM
|
||||||
add wave -noupdate -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState
|
add wave -noupdate -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState
|
||||||
add wave -noupdate -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall
|
add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadM
|
||||||
add wave -noupdate -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWRead
|
add wave -noupdate -expand -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall
|
||||||
add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF
|
add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadPTE
|
||||||
add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM
|
add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE
|
||||||
add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF
|
add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF
|
||||||
add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM
|
add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM
|
||||||
add wave -noupdate -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE
|
add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF
|
||||||
add wave -noupdate -group ptwalker -divider data
|
add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM
|
||||||
add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF
|
add wave -noupdate -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE
|
||||||
add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM
|
add wave -noupdate -expand -group ptwalker -divider data
|
||||||
add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF
|
add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF
|
||||||
add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM
|
add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM
|
||||||
add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM
|
add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF
|
||||||
add wave -noupdate -group {LSU ARB} -group lsu -color Gold /testbench/dut/hart/lsu/arbiter/CurrState
|
add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM
|
||||||
add wave -noupdate -group {LSU ARB} -group lsu -color {Medium Orchid} /testbench/dut/hart/lsu/arbiter/SelPTW
|
add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM
|
||||||
add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWTranslate
|
add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/MemAdrM
|
||||||
add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWRead
|
add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/lsu/MemPAdrM
|
||||||
add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWPAdr
|
add wave -noupdate -expand -group {LSU ARB} -expand -group lsu -color Gold /testbench/dut/hart/lsu/arbiter/CurrState
|
||||||
add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWReadPTE
|
add wave -noupdate -expand -group {LSU ARB} -expand -group lsu -color {Medium Orchid} /testbench/dut/hart/lsu/arbiter/SelPTW
|
||||||
|
add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWTranslate
|
||||||
|
add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWReadPTE
|
||||||
add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW
|
add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW
|
||||||
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HCLK
|
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HCLK
|
||||||
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESETn
|
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESETn
|
||||||
@ -395,13 +416,15 @@ add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genb
|
|||||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/TXRDYb
|
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/TXRDYb
|
||||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/RXRDYb
|
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/RXRDYb
|
||||||
add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
|
add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
|
||||||
add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HCLK
|
add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HCLK
|
||||||
add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HSELUART
|
add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HSELUART
|
||||||
add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HADDR
|
add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HADDR
|
||||||
add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HWRITE
|
add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWRITE
|
||||||
add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HWDATA
|
add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWDATA
|
||||||
|
add wave -noupdate /testbench/dut/hart/lsu/dcache/OFFSETLEN
|
||||||
|
add wave -noupdate /testbench/dut/hart/lsu/dcache/INDEXLEN
|
||||||
TreeUpdate [SetDefaultTree]
|
TreeUpdate [SetDefaultTree]
|
||||||
WaveRestoreCursors {{Cursor 12} {4076 ns} 0} {{Cursor 4} {8790617 ns} 0}
|
WaveRestoreCursors {{Cursor 3} {21755 ns} 0} {{Cursor 4} {15501 ns} 0}
|
||||||
quietly wave cursor active 1
|
quietly wave cursor active 1
|
||||||
configure wave -namecolwidth 250
|
configure wave -namecolwidth 250
|
||||||
configure wave -valuecolwidth 297
|
configure wave -valuecolwidth 297
|
||||||
@ -417,4 +440,4 @@ configure wave -griddelta 40
|
|||||||
configure wave -timeline 0
|
configure wave -timeline 0
|
||||||
configure wave -timelineunits ns
|
configure wave -timelineunits ns
|
||||||
update
|
update
|
||||||
WaveRestoreZoom {4026 ns} {4254 ns}
|
WaveRestoreZoom {21597 ns} {21891 ns}
|
||||||
|
|||||||
14
wally-pipelined/src/cache/dcache.sv
vendored
14
wally-pipelined/src/cache/dcache.sv
vendored
@ -43,6 +43,7 @@ module dcache
|
|||||||
|
|
||||||
input logic [`XLEN-1:0] WriteDataM,
|
input logic [`XLEN-1:0] WriteDataM,
|
||||||
output logic [`XLEN-1:0] ReadDataW,
|
output logic [`XLEN-1:0] ReadDataW,
|
||||||
|
output logic [`XLEN-1:0] ReadDataM,
|
||||||
output logic DCacheStall,
|
output logic DCacheStall,
|
||||||
output logic CommittedM,
|
output logic CommittedM,
|
||||||
|
|
||||||
@ -131,6 +132,7 @@ module dcache
|
|||||||
logic CntEn;
|
logic CntEn;
|
||||||
logic CntReset;
|
logic CntReset;
|
||||||
logic CPUBusy, PreviousCPUBusy;
|
logic CPUBusy, PreviousCPUBusy;
|
||||||
|
logic SelEvict;
|
||||||
|
|
||||||
|
|
||||||
typedef enum {STATE_READY,
|
typedef enum {STATE_READY,
|
||||||
@ -297,16 +299,22 @@ module dcache
|
|||||||
// which means the CPU is ready to take data. Or if the CPU just became
|
// which means the CPU is ready to take data. Or if the CPU just became
|
||||||
// busy. Then when we exit CPU_BUSY we want to ensure the data is not
|
// busy. Then when we exit CPU_BUSY we want to ensure the data is not
|
||||||
// updated, this is ~PreviousCPUBusy.
|
// updated, this is ~PreviousCPUBusy.
|
||||||
|
// also must update if cpu stalled and processing a read miss
|
||||||
|
// which occurs if in state miss read word delay.
|
||||||
assign CPUBusy = CurrState == STATE_CPU_BUSY;
|
assign CPUBusy = CurrState == STATE_CPU_BUSY;
|
||||||
flop #(1) CPUBusyReg(.clk, .d(CPUBusy), .q(PreviousCPUBusy));
|
flop #(1) CPUBusyReg(.clk, .d(CPUBusy), .q(PreviousCPUBusy));
|
||||||
|
|
||||||
assign ReadDataWEn = (~StallW & ~PreviousCPUBusy) | (NextState == STATE_CPU_BUSY & CurrState == STATE_READY);
|
assign ReadDataWEn = (~StallW & ~PreviousCPUBusy) |
|
||||||
|
(NextState == STATE_CPU_BUSY & CurrState == STATE_READY) |
|
||||||
|
(CurrState == STATE_MISS_READ_WORD_DELAY);
|
||||||
|
|
||||||
flopen #(`XLEN) ReadDataWReg(.clk(clk),
|
flopen #(`XLEN) ReadDataWReg(.clk(clk),
|
||||||
.en(ReadDataWEn),
|
.en(ReadDataWEn),
|
||||||
.d(FinalReadDataWordM),
|
.d(FinalReadDataWordM),
|
||||||
.q(ReadDataW));
|
.q(ReadDataW));
|
||||||
|
|
||||||
|
assign ReadDataM = FinalReadDataWordM;
|
||||||
|
|
||||||
// write path
|
// write path
|
||||||
subwordwrite subwordwrite(.HRDATA(ReadDataWordM),
|
subwordwrite subwordwrite(.HRDATA(ReadDataWordM),
|
||||||
.HADDRD(MemPAdrM[2:0]),
|
.HADDRD(MemPAdrM[2:0]),
|
||||||
@ -340,7 +348,7 @@ module dcache
|
|||||||
// *** optimize this
|
// *** optimize this
|
||||||
mux2 #(`PA_BITS) BaseAdrMux(.d0(MemPAdrM),
|
mux2 #(`PA_BITS) BaseAdrMux(.d0(MemPAdrM),
|
||||||
.d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
|
.d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
|
||||||
.s(AHBWrite & CacheableM),
|
.s(SelEvict),
|
||||||
.y(BasePAdrM));
|
.y(BasePAdrM));
|
||||||
|
|
||||||
assign BasePAdrOffsetM = CacheableM ? {{OFFSETLEN}{1'b0}} : BasePAdrM[OFFSETLEN-1:0];
|
assign BasePAdrOffsetM = CacheableM ? {{OFFSETLEN}{1'b0}} : BasePAdrM[OFFSETLEN-1:0];
|
||||||
@ -420,6 +428,7 @@ module dcache
|
|||||||
SelAMOWrite = 1'b0;
|
SelAMOWrite = 1'b0;
|
||||||
CommittedM = 1'b0;
|
CommittedM = 1'b0;
|
||||||
SelUncached = 1'b0;
|
SelUncached = 1'b0;
|
||||||
|
SelEvict = 1'b0;
|
||||||
|
|
||||||
case (CurrState)
|
case (CurrState)
|
||||||
STATE_READY: begin
|
STATE_READY: begin
|
||||||
@ -562,6 +571,7 @@ module dcache
|
|||||||
AHBWrite = 1'b1;
|
AHBWrite = 1'b1;
|
||||||
SelAdrM = 1'b1;
|
SelAdrM = 1'b1;
|
||||||
CommittedM = 1'b1;
|
CommittedM = 1'b1;
|
||||||
|
SelEvict = 1'b1;
|
||||||
if( FetchCountFlag & AHBAck) begin
|
if( FetchCountFlag & AHBAck) begin
|
||||||
NextState = STATE_MISS_WRITE_CACHE_BLOCK;
|
NextState = STATE_MISS_WRITE_CACHE_BLOCK;
|
||||||
end else begin
|
end else begin
|
||||||
|
|||||||
@ -129,9 +129,10 @@ module lsu
|
|||||||
logic [`XLEN-1:0] HPTWReadPTE;
|
logic [`XLEN-1:0] HPTWReadPTE;
|
||||||
logic MMUReady;
|
logic MMUReady;
|
||||||
logic HPTWStall;
|
logic HPTWStall;
|
||||||
logic [`XLEN-1:0] HPTWPAdr;
|
logic [`XLEN-1:0] HPTWPAdrE;
|
||||||
|
logic [`XLEN-1:0] HPTWPAdrM;
|
||||||
logic HPTWTranslate;
|
logic HPTWTranslate;
|
||||||
logic HPTWRead;
|
logic HPTWReadM;
|
||||||
logic [1:0] MemRWMtoDCache;
|
logic [1:0] MemRWMtoDCache;
|
||||||
logic [2:0] Funct3MtoDCache;
|
logic [2:0] Funct3MtoDCache;
|
||||||
logic [1:0] AtomicMtoDCache;
|
logic [1:0] AtomicMtoDCache;
|
||||||
@ -146,6 +147,8 @@ module lsu
|
|||||||
logic DCacheStall;
|
logic DCacheStall;
|
||||||
|
|
||||||
logic CacheableM;
|
logic CacheableM;
|
||||||
|
logic CacheableMtoDCache;
|
||||||
|
logic SelPTW;
|
||||||
|
|
||||||
logic CommittedMfromDCache;
|
logic CommittedMfromDCache;
|
||||||
logic PendingInterruptMtoDCache;
|
logic PendingInterruptMtoDCache;
|
||||||
@ -169,9 +172,10 @@ module lsu
|
|||||||
.HPTWReadPTE(HPTWReadPTE),
|
.HPTWReadPTE(HPTWReadPTE),
|
||||||
.MMUReady(HPTWReady),
|
.MMUReady(HPTWReady),
|
||||||
.HPTWStall(HPTWStall),
|
.HPTWStall(HPTWStall),
|
||||||
.HPTWPAdr(HPTWPAdr),
|
.HPTWPAdrE(HPTWPAdrE),
|
||||||
|
.HPTWPAdrM(HPTWPAdrM),
|
||||||
.HPTWTranslate(HPTWTranslate),
|
.HPTWTranslate(HPTWTranslate),
|
||||||
.HPTWRead(HPTWRead),
|
.HPTWReadM(HPTWReadM),
|
||||||
.WalkerInstrPageFaultF(WalkerInstrPageFaultF),
|
.WalkerInstrPageFaultF(WalkerInstrPageFaultF),
|
||||||
.WalkerLoadPageFaultM(WalkerLoadPageFaultM),
|
.WalkerLoadPageFaultM(WalkerLoadPageFaultM),
|
||||||
.WalkerStorePageFaultM(WalkerStorePageFaultM));
|
.WalkerStorePageFaultM(WalkerStorePageFaultM));
|
||||||
@ -183,15 +187,17 @@ module lsu
|
|||||||
.reset(reset),
|
.reset(reset),
|
||||||
// HPTW connection
|
// HPTW connection
|
||||||
.HPTWTranslate(HPTWTranslate),
|
.HPTWTranslate(HPTWTranslate),
|
||||||
.HPTWRead(HPTWRead),
|
.HPTWReadM(HPTWReadM),
|
||||||
.HPTWPAdr(HPTWPAdr),
|
.HPTWPAdrE(HPTWPAdrE),
|
||||||
.HPTWReadPTE(HPTWReadPTE),
|
.HPTWPAdrM(HPTWPAdrM),
|
||||||
|
//.HPTWReadPTE(HPTWReadPTE),
|
||||||
.HPTWStall(HPTWStall),
|
.HPTWStall(HPTWStall),
|
||||||
// CPU connection
|
// CPU connection
|
||||||
.MemRWM(MemRWM),
|
.MemRWM(MemRWM),
|
||||||
.Funct3M(Funct3M),
|
.Funct3M(Funct3M),
|
||||||
.AtomicM(AtomicM),
|
.AtomicM(AtomicM),
|
||||||
.MemAdrM(MemAdrM),
|
.MemAdrM(MemAdrM),
|
||||||
|
.MemAdrE(MemAdrE),
|
||||||
.CommittedM(CommittedM),
|
.CommittedM(CommittedM),
|
||||||
.PendingInterruptM(PendingInterruptM),
|
.PendingInterruptM(PendingInterruptM),
|
||||||
.StallW(StallW),
|
.StallW(StallW),
|
||||||
@ -205,13 +211,15 @@ module lsu
|
|||||||
.Funct3MtoDCache(Funct3MtoDCache),
|
.Funct3MtoDCache(Funct3MtoDCache),
|
||||||
.AtomicMtoDCache(AtomicMtoDCache),
|
.AtomicMtoDCache(AtomicMtoDCache),
|
||||||
.MemAdrMtoDCache(MemAdrMtoDCache),
|
.MemAdrMtoDCache(MemAdrMtoDCache),
|
||||||
|
.MemAdrEtoDCache(MemAdrEtoDCache),
|
||||||
.StallWtoDCache(StallWtoDCache),
|
.StallWtoDCache(StallWtoDCache),
|
||||||
.SquashSCWfromDCache(SquashSCWfromDCache),
|
.SquashSCWfromDCache(SquashSCWfromDCache),
|
||||||
.DataMisalignedMfromDCache(DataMisalignedMfromDCache),
|
.DataMisalignedMfromDCache(DataMisalignedMfromDCache),
|
||||||
.ReadDataWfromDCache(ReadDataWfromDCache),
|
.ReadDataWfromDCache(ReadDataWfromDCache),
|
||||||
.CommittedMfromDCache(CommittedMfromDCache),
|
.CommittedMfromDCache(CommittedMfromDCache),
|
||||||
.PendingInterruptMtoDCache(PendingInterruptMtoDCache),
|
.PendingInterruptMtoDCache(PendingInterruptMtoDCache),
|
||||||
.DCacheStall(DCacheStall));
|
.DCacheStall(DCacheStall),
|
||||||
|
.SelPTW(SelPTW));
|
||||||
|
|
||||||
|
|
||||||
mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
|
mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
|
||||||
@ -239,10 +247,10 @@ module lsu
|
|||||||
// .SelRegions(DHSELRegionsM),
|
// .SelRegions(DHSELRegionsM),
|
||||||
.*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist?
|
.*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist?
|
||||||
|
|
||||||
|
assign CacheableMtoDCache = SelPTW ? 1'b1 : CacheableM;
|
||||||
generate
|
generate
|
||||||
if (`XLEN == 32) assign DCtoAHBSizeM = CacheableM ? 3'b010 : Funct3MtoDCache;
|
if (`XLEN == 32) assign DCtoAHBSizeM = CacheableMtoDCache ? 3'b010 : Funct3MtoDCache;
|
||||||
else assign DCtoAHBSizeM = CacheableM ? 3'b011 : Funct3MtoDCache;
|
else assign DCtoAHBSizeM = CacheableMtoDCache ? 3'b011 : Funct3MtoDCache;
|
||||||
endgenerate;
|
endgenerate;
|
||||||
|
|
||||||
|
|
||||||
@ -309,30 +317,27 @@ module lsu
|
|||||||
assign LoadMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoDCache[1];
|
assign LoadMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoDCache[1];
|
||||||
assign StoreMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoDCache[0];
|
assign StoreMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoDCache[0];
|
||||||
|
|
||||||
// *** BUG
|
|
||||||
assign MemAdrEtoDCache = MemAdrE; // needs to be muxed in lsuarb.
|
|
||||||
|
|
||||||
|
|
||||||
dcache dcache(.clk(clk),
|
dcache dcache(.clk(clk),
|
||||||
.reset(reset),
|
.reset(reset),
|
||||||
.StallM(StallM),
|
.StallM(StallM),
|
||||||
.StallW(StallW),
|
.StallW(StallWtoDCache),
|
||||||
.FlushM(FlushM),
|
.FlushM(FlushM),
|
||||||
.FlushW(FlushW),
|
.FlushW(FlushWtoDCache),
|
||||||
.MemRWM(MemRWMtoDCache),
|
.MemRWM(MemRWMtoDCache),
|
||||||
.Funct3M(Funct3MtoDCache),
|
.Funct3M(Funct3MtoDCache),
|
||||||
.Funct7M(Funct7M),
|
.Funct7M(Funct7M),
|
||||||
.AtomicM(AtomicMtoDCache),
|
.AtomicM(AtomicMtoDCache),
|
||||||
.MemAdrE(MemAdrEtoDCache), // *** add to arb
|
.MemAdrE(MemAdrEtoDCache),
|
||||||
.MemPAdrM(MemPAdrM),
|
.MemPAdrM(MemPAdrM),
|
||||||
.WriteDataM(WriteDataM),
|
.WriteDataM(WriteDataM),
|
||||||
.ReadDataW(ReadDataWfromDCache),
|
.ReadDataW(ReadDataWfromDCache),
|
||||||
|
.ReadDataM(HPTWReadPTE),
|
||||||
.DCacheStall(DCacheStall),
|
.DCacheStall(DCacheStall),
|
||||||
.CommittedM(CommittedMfromDCache),
|
.CommittedM(CommittedMfromDCache),
|
||||||
.ExceptionM(ExceptionM),
|
.ExceptionM(ExceptionM),
|
||||||
.PendingInterruptM(PendingInterruptMtoDCache),
|
.PendingInterruptM(PendingInterruptMtoDCache),
|
||||||
.DTLBMissM(DTLBMissM),
|
.DTLBMissM(DTLBMissM),
|
||||||
.CacheableM(CacheableM),
|
.CacheableM(CacheableMtoDCache),
|
||||||
.DTLBWriteM(DTLBWriteM),
|
.DTLBWriteM(DTLBWriteM),
|
||||||
|
|
||||||
// AHB connection
|
// AHB connection
|
||||||
|
|||||||
@ -31,10 +31,11 @@ module lsuArb
|
|||||||
|
|
||||||
// from page table walker
|
// from page table walker
|
||||||
input logic HPTWTranslate,
|
input logic HPTWTranslate,
|
||||||
input logic HPTWRead,
|
input logic HPTWReadM,
|
||||||
input logic [`XLEN-1:0] HPTWPAdr,
|
input logic [`XLEN-1:0] HPTWPAdrE,
|
||||||
|
input logic [`XLEN-1:0] HPTWPAdrM,
|
||||||
// to page table walker.
|
// to page table walker.
|
||||||
output logic [`XLEN-1:0] HPTWReadPTE,
|
//output logic [`XLEN-1:0] HPTWReadPTE,
|
||||||
output logic HPTWStall,
|
output logic HPTWStall,
|
||||||
|
|
||||||
// from CPU
|
// from CPU
|
||||||
@ -42,6 +43,7 @@ module lsuArb
|
|||||||
input logic [2:0] Funct3M,
|
input logic [2:0] Funct3M,
|
||||||
input logic [1:0] AtomicM,
|
input logic [1:0] AtomicM,
|
||||||
input logic [`XLEN-1:0] MemAdrM,
|
input logic [`XLEN-1:0] MemAdrM,
|
||||||
|
input logic [`XLEN-1:0] MemAdrE,
|
||||||
input logic StallW,
|
input logic StallW,
|
||||||
input logic PendingInterruptM,
|
input logic PendingInterruptM,
|
||||||
// to CPU
|
// to CPU
|
||||||
@ -57,8 +59,11 @@ module lsuArb
|
|||||||
output logic [2:0] Funct3MtoDCache,
|
output logic [2:0] Funct3MtoDCache,
|
||||||
output logic [1:0] AtomicMtoDCache,
|
output logic [1:0] AtomicMtoDCache,
|
||||||
output logic [`XLEN-1:0] MemAdrMtoDCache,
|
output logic [`XLEN-1:0] MemAdrMtoDCache,
|
||||||
|
output logic [`XLEN-1:0] MemAdrEtoDCache,
|
||||||
output logic StallWtoDCache,
|
output logic StallWtoDCache,
|
||||||
output logic PendingInterruptMtoDCache,
|
output logic PendingInterruptMtoDCache,
|
||||||
|
output logic SelPTW,
|
||||||
|
|
||||||
|
|
||||||
// from D Cache
|
// from D Cache
|
||||||
input logic CommittedMfromDCache,
|
input logic CommittedMfromDCache,
|
||||||
@ -86,7 +91,6 @@ module lsuArb
|
|||||||
|
|
||||||
|
|
||||||
statetype CurrState, NextState;
|
statetype CurrState, NextState;
|
||||||
logic SelPTW;
|
|
||||||
logic [2:0] PTWSize;
|
logic [2:0] PTWSize;
|
||||||
|
|
||||||
|
|
||||||
@ -136,7 +140,7 @@ module lsuArb
|
|||||||
// multiplex the outputs to LSU
|
// multiplex the outputs to LSU
|
||||||
assign DisableTranslation = SelPTW; // change names between SelPTW would be confusing in DTLB.
|
assign DisableTranslation = SelPTW; // change names between SelPTW would be confusing in DTLB.
|
||||||
assign SelPTW = (CurrState == StatePTWActive && HPTWTranslate) || (CurrState == StateReady && HPTWTranslate);
|
assign SelPTW = (CurrState == StatePTWActive && HPTWTranslate) || (CurrState == StateReady && HPTWTranslate);
|
||||||
assign MemRWMtoDCache = SelPTW ? {HPTWRead, 1'b0} : MemRWM;
|
assign MemRWMtoDCache = SelPTW ? {HPTWReadM, 1'b0} : MemRWM;
|
||||||
|
|
||||||
generate
|
generate
|
||||||
assign PTWSize = (`XLEN==32 ? 3'b010 : 3'b011); // 32 or 64-bit access from htpw
|
assign PTWSize = (`XLEN==32 ? 3'b010 : 3'b011); // 32 or 64-bit access from htpw
|
||||||
@ -144,7 +148,8 @@ module lsuArb
|
|||||||
mux2 #(3) sizemux(Funct3M, PTWSize, SelPTW, Funct3MtoDCache);
|
mux2 #(3) sizemux(Funct3M, PTWSize, SelPTW, Funct3MtoDCache);
|
||||||
|
|
||||||
assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM;
|
assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM;
|
||||||
assign MemAdrMtoDCache = SelPTW ? HPTWPAdr : MemAdrM;
|
assign MemAdrMtoDCache = SelPTW ? HPTWPAdrM : MemAdrM;
|
||||||
|
assign MemAdrEtoDCache = SelPTW ? HPTWPAdrE : MemAdrE;
|
||||||
assign StallWtoDCache = SelPTW ? 1'b0 : StallW;
|
assign StallWtoDCache = SelPTW ? 1'b0 : StallW;
|
||||||
// always block interrupts when using the hardware page table walker.
|
// always block interrupts when using the hardware page table walker.
|
||||||
assign CommittedM = SelPTW ? 1'b1 : CommittedMfromDCache;
|
assign CommittedM = SelPTW ? 1'b1 : CommittedMfromDCache;
|
||||||
@ -152,7 +157,7 @@ module lsuArb
|
|||||||
// demux the inputs from LSU to walker or cpu's data port.
|
// demux the inputs from LSU to walker or cpu's data port.
|
||||||
|
|
||||||
assign ReadDataW = SelPTW ? `XLEN'b0 : ReadDataWfromDCache; // probably can avoid this demux
|
assign ReadDataW = SelPTW ? `XLEN'b0 : ReadDataWfromDCache; // probably can avoid this demux
|
||||||
assign HPTWReadPTE = SelPTW ? ReadDataWfromDCache : `XLEN'b0 ; // probably can avoid this demux
|
//assign HPTWReadPTE = SelPTW ? ReadDataWfromDCache : `XLEN'b0 ; // probably can avoid this demux
|
||||||
assign SquashSCW = SelPTW ? 1'b0 : SquashSCWfromDCache;
|
assign SquashSCW = SelPTW ? 1'b0 : SquashSCWfromDCache;
|
||||||
assign DataMisalignedM = SelPTW ? 1'b0 : DataMisalignedMfromDCache;
|
assign DataMisalignedM = SelPTW ? 1'b0 : DataMisalignedMfromDCache;
|
||||||
// *** need to rename DcacheStall and Datastall.
|
// *** need to rename DcacheStall and Datastall.
|
||||||
|
|||||||
@ -59,9 +59,10 @@ module pagetablewalker
|
|||||||
input logic HPTWStall,
|
input logic HPTWStall,
|
||||||
|
|
||||||
// *** modify to send to LSU
|
// *** modify to send to LSU
|
||||||
output logic [`XLEN-1:0] HPTWPAdr, // this probalby should be `PA_BITS wide
|
output logic [`XLEN-1:0] HPTWPAdrE, // this probalby should be `PA_BITS wide
|
||||||
|
output logic [`XLEN-1:0] HPTWPAdrM, // this probalby should be `PA_BITS wide
|
||||||
output logic HPTWTranslate, // *** rename to HPTWReq
|
output logic HPTWTranslate, // *** rename to HPTWReq
|
||||||
output logic HPTWRead,
|
output logic HPTWReadM,
|
||||||
|
|
||||||
|
|
||||||
// Faults
|
// Faults
|
||||||
@ -70,50 +71,61 @@ module pagetablewalker
|
|||||||
output logic WalkerStorePageFaultM
|
output logic WalkerStorePageFaultM
|
||||||
);
|
);
|
||||||
|
|
||||||
|
logic HPTWReadE;
|
||||||
|
|
||||||
generate
|
generate
|
||||||
if (`MEM_VIRTMEM) begin
|
if (`MEM_VIRTMEM) begin
|
||||||
// Internal signals
|
// Internal signals
|
||||||
// register TLBs translation miss requests
|
// register TLBs translation miss requests
|
||||||
logic [`XLEN-1:0] TranslationVAdrQ;
|
logic [`XLEN-1:0] TranslationVAdrQ;
|
||||||
logic ITLBMissFQ, DTLBMissMQ;
|
logic ITLBMissFQ, DTLBMissMQ;
|
||||||
|
|
||||||
logic [`PPN_BITS-1:0] BasePageTablePPN;
|
logic [`PPN_BITS-1:0] BasePageTablePPN;
|
||||||
logic [`XLEN-1:0] TranslationVAdr;
|
logic [`XLEN-1:0] TranslationVAdr;
|
||||||
logic [`XLEN-1:0] SavedPTE, CurrentPTE;
|
logic [`XLEN-1:0] SavedPTE, CurrentPTE;
|
||||||
logic [`PA_BITS-1:0] TranslationPAdr;
|
logic [`PA_BITS-1:0] TranslationPAdr;
|
||||||
logic [`PPN_BITS-1:0] CurrentPPN;
|
logic [`PPN_BITS-1:0] CurrentPPN;
|
||||||
logic [`SVMODE_BITS-1:0] SvMode;
|
logic [`SVMODE_BITS-1:0] SvMode;
|
||||||
logic MemStore;
|
logic MemStore;
|
||||||
|
|
||||||
// PTE Control Bits
|
// PTE Control Bits
|
||||||
logic Dirty, Accessed, Global, User,
|
logic Dirty, Accessed, Global, User,
|
||||||
Executable, Writable, Readable, Valid;
|
Executable, Writable, Readable, Valid;
|
||||||
// PTE descriptions
|
// PTE descriptions
|
||||||
logic ValidPTE, AccessAlert, MegapageMisaligned, BadMegapage, LeafPTE;
|
logic ValidPTE, AccessAlert, MegapageMisaligned, BadMegapage, LeafPTE;
|
||||||
|
|
||||||
// Outputs of walker
|
// Outputs of walker
|
||||||
logic [`XLEN-1:0] PageTableEntry;
|
logic [`XLEN-1:0] PageTableEntry;
|
||||||
logic [1:0] PageType;
|
logic [1:0] PageType;
|
||||||
logic StartWalk;
|
logic StartWalk;
|
||||||
logic EndWalk;
|
logic EndWalk;
|
||||||
|
|
||||||
typedef enum {LEVEL0_WDV,
|
typedef enum {LEVEL0_WDV,
|
||||||
LEVEL0,
|
LEVEL0,
|
||||||
LEVEL1_WDV,
|
LEVEL1_WDV,
|
||||||
LEVEL1,
|
LEVEL1,
|
||||||
LEVEL2_WDV,
|
LEVEL2_WDV,
|
||||||
LEVEL2,
|
LEVEL2,
|
||||||
LEVEL3_WDV,
|
LEVEL3_WDV,
|
||||||
LEVEL3,
|
LEVEL3,
|
||||||
LEAF,
|
LEAF,
|
||||||
IDLE,
|
IDLE,
|
||||||
START,
|
START,
|
||||||
FAULT} statetype;
|
FAULT} statetype;
|
||||||
|
|
||||||
statetype WalkerState, NextWalkerState;
|
statetype WalkerState, NextWalkerState;
|
||||||
|
|
||||||
logic PRegEn;
|
logic PRegEn;
|
||||||
logic SelDataTranslation;
|
logic SelDataTranslation;
|
||||||
|
|
||||||
|
|
||||||
|
flop #(`XLEN) HPTWPAdrMReg(.clk(clk),
|
||||||
|
.d(HPTWPAdrE),
|
||||||
|
.q(HPTWPAdrM));
|
||||||
|
|
||||||
|
flop #(1) HPTWReadMReg(.clk(clk),
|
||||||
|
.d(HPTWReadE),
|
||||||
|
.q(HPTWReadM));
|
||||||
|
|
||||||
|
|
||||||
assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
|
assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
|
||||||
@ -128,35 +140,35 @@ module pagetablewalker
|
|||||||
|
|
||||||
flopenr #(`XLEN)
|
flopenr #(`XLEN)
|
||||||
TranslationVAdrReg(.clk(clk),
|
TranslationVAdrReg(.clk(clk),
|
||||||
.reset(reset),
|
.reset(reset),
|
||||||
.en(StartWalk),
|
.en(StartWalk),
|
||||||
.d(TranslationVAdr),
|
.d(TranslationVAdr),
|
||||||
.q(TranslationVAdrQ));
|
.q(TranslationVAdrQ));
|
||||||
|
|
||||||
flopenrc #(1)
|
flopenrc #(1)
|
||||||
DTLBMissMReg(.clk(clk),
|
DTLBMissMReg(.clk(clk),
|
||||||
.reset(reset),
|
.reset(reset),
|
||||||
.en(StartWalk | EndWalk),
|
.en(StartWalk | EndWalk),
|
||||||
.clear(EndWalk),
|
.clear(EndWalk),
|
||||||
.d(DTLBMissM),
|
.d(DTLBMissM),
|
||||||
.q(DTLBMissMQ));
|
.q(DTLBMissMQ));
|
||||||
|
|
||||||
flopenrc #(1)
|
flopenrc #(1)
|
||||||
ITLBMissMReg(.clk(clk),
|
ITLBMissMReg(.clk(clk),
|
||||||
.reset(reset),
|
.reset(reset),
|
||||||
.en(StartWalk | EndWalk),
|
.en(StartWalk | EndWalk),
|
||||||
.clear(EndWalk),
|
.clear(EndWalk),
|
||||||
.d(ITLBMissF),
|
.d(ITLBMissF),
|
||||||
.q(ITLBMissFQ));
|
.q(ITLBMissFQ));
|
||||||
|
|
||||||
|
|
||||||
assign StartWalk = WalkerState == IDLE && (DTLBMissM | ITLBMissF);
|
assign StartWalk = WalkerState == IDLE && (DTLBMissM | ITLBMissF);
|
||||||
assign EndWalk = WalkerState == LEAF ||
|
assign EndWalk = WalkerState == LEAF ||
|
||||||
//(WalkerState == LEVEL0 && ValidPTE && LeafPTE && ~AccessAlert) ||
|
//(WalkerState == LEVEL0 && ValidPTE && LeafPTE && ~AccessAlert) ||
|
||||||
(WalkerState == LEVEL1 && ValidPTE && LeafPTE && ~AccessAlert) ||
|
(WalkerState == LEVEL1 && ValidPTE && LeafPTE && ~AccessAlert) ||
|
||||||
(WalkerState == LEVEL2 && ValidPTE && LeafPTE && ~AccessAlert) ||
|
(WalkerState == LEVEL2 && ValidPTE && LeafPTE && ~AccessAlert) ||
|
||||||
(WalkerState == LEVEL3 && ValidPTE && LeafPTE && ~AccessAlert) ||
|
(WalkerState == LEVEL3 && ValidPTE && LeafPTE && ~AccessAlert) ||
|
||||||
(WalkerState == FAULT);
|
(WalkerState == FAULT);
|
||||||
|
|
||||||
assign HPTWTranslate = (DTLBMissMQ | ITLBMissFQ) & ~EndWalk;
|
assign HPTWTranslate = (DTLBMissMQ | ITLBMissFQ) & ~EndWalk;
|
||||||
//assign HPTWTranslate = DTLBMissM | ITLBMissF;
|
//assign HPTWTranslate = DTLBMissM | ITLBMissF;
|
||||||
@ -177,385 +189,389 @@ module pagetablewalker
|
|||||||
assign PageTypeM = PageType;
|
assign PageTypeM = PageType;
|
||||||
|
|
||||||
|
|
||||||
// generate
|
// generate
|
||||||
if (`XLEN == 32) begin
|
if (`XLEN == 32) begin
|
||||||
logic [9:0] VPN1, VPN0;
|
logic [9:0] VPN1, VPN0;
|
||||||
|
|
||||||
flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
|
flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
|
||||||
|
|
||||||
/* -----\/----- EXCLUDED -----\/-----
|
/* -----\/----- EXCLUDED -----\/-----
|
||||||
assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV) && ~HPTWStall;
|
assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV) && ~HPTWStall;
|
||||||
-----/\----- EXCLUDED -----/\----- */
|
-----/\----- EXCLUDED -----/\----- */
|
||||||
|
|
||||||
// State transition logic
|
// State transition logic
|
||||||
always_comb begin
|
always_comb begin
|
||||||
PRegEn = 1'b0;
|
PRegEn = 1'b0;
|
||||||
TranslationPAdr = '0;
|
TranslationPAdr = '0;
|
||||||
HPTWRead = 1'b0;
|
HPTWReadE = 1'b0;
|
||||||
PageTableEntry = '0;
|
PageTableEntry = '0;
|
||||||
PageType = '0;
|
PageType = '0;
|
||||||
DTLBWriteM = '0;
|
DTLBWriteM = '0;
|
||||||
ITLBWriteF = '0;
|
ITLBWriteF = '0;
|
||||||
|
|
||||||
WalkerInstrPageFaultF = 1'b0;
|
WalkerInstrPageFaultF = 1'b0;
|
||||||
WalkerLoadPageFaultM = 1'b0;
|
WalkerLoadPageFaultM = 1'b0;
|
||||||
WalkerStorePageFaultM = 1'b0;
|
WalkerStorePageFaultM = 1'b0;
|
||||||
|
|
||||||
case (WalkerState)
|
case (WalkerState)
|
||||||
IDLE: begin
|
IDLE: begin
|
||||||
if (HPTWTranslate && SvMode == `SV32) begin // *** Added SvMode
|
if (HPTWTranslate && SvMode == `SV32) begin // *** Added SvMode
|
||||||
NextWalkerState = START;
|
NextWalkerState = START;
|
||||||
end else begin
|
end else begin
|
||||||
NextWalkerState = IDLE;
|
NextWalkerState = IDLE;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
START: begin
|
START: begin
|
||||||
NextWalkerState = LEVEL1_WDV;
|
NextWalkerState = LEVEL1_WDV;
|
||||||
TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00};
|
TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00};
|
||||||
HPTWRead = 1'b1;
|
HPTWReadE = 1'b1;
|
||||||
end
|
end
|
||||||
|
|
||||||
LEVEL1_WDV: begin
|
LEVEL1_WDV: begin
|
||||||
TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00};
|
TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00};
|
||||||
if (HPTWStall) begin
|
HPTWReadE = 1'b1;
|
||||||
NextWalkerState = LEVEL1_WDV;
|
if (HPTWStall) begin
|
||||||
end else begin
|
NextWalkerState = LEVEL1_WDV;
|
||||||
NextWalkerState = LEVEL1;
|
end else begin
|
||||||
PRegEn = 1'b1;
|
NextWalkerState = LEVEL1;
|
||||||
end
|
PRegEn = 1'b1;
|
||||||
end
|
end
|
||||||
|
end
|
||||||
|
|
||||||
LEVEL1: begin
|
LEVEL1: begin
|
||||||
// *** <FUTURE WORK> According to the architecture, we should
|
// *** <FUTURE WORK> According to the architecture, we should
|
||||||
// fault upon finding a superpage that is misaligned or has 0
|
// fault upon finding a superpage that is misaligned or has 0
|
||||||
// access bit. The following commented line of code is
|
// access bit. The following commented line of code is
|
||||||
// supposed to perform that check. However, it is untested.
|
// supposed to perform that check. However, it is untested.
|
||||||
if (ValidPTE && LeafPTE && ~BadMegapage) begin
|
if (ValidPTE && LeafPTE && ~BadMegapage) begin
|
||||||
NextWalkerState = LEAF;
|
NextWalkerState = LEAF;
|
||||||
PageTableEntry = CurrentPTE;
|
PageTableEntry = CurrentPTE;
|
||||||
PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux?
|
PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux?
|
||||||
DTLBWriteM = DTLBMissMQ;
|
DTLBWriteM = DTLBMissMQ;
|
||||||
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
|
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
|
||||||
TranslationPAdr = {2'b00, TranslationVAdrQ[31:0]};
|
TranslationPAdr = {2'b00, TranslationVAdr[31:0]};
|
||||||
end
|
end
|
||||||
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
|
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
|
||||||
else if (ValidPTE && ~LeafPTE) begin
|
else if (ValidPTE && ~LeafPTE) begin
|
||||||
NextWalkerState = LEVEL0_WDV;
|
NextWalkerState = LEVEL0_WDV;
|
||||||
TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
|
|
||||||
HPTWRead = 1'b1;
|
|
||||||
end else begin
|
|
||||||
NextWalkerState = FAULT;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
LEVEL0_WDV: begin
|
|
||||||
TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
|
TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
|
||||||
if (HPTWStall) begin
|
HPTWReadE = 1'b1;
|
||||||
NextWalkerState = LEVEL0_WDV;
|
end else begin
|
||||||
end else begin
|
NextWalkerState = FAULT;
|
||||||
NextWalkerState = LEVEL0;
|
end
|
||||||
PRegEn = 1'b1;
|
end
|
||||||
end
|
|
||||||
|
LEVEL0_WDV: begin
|
||||||
|
TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
|
||||||
|
HPTWReadE = 1'b1;
|
||||||
|
if (HPTWStall) begin
|
||||||
|
NextWalkerState = LEVEL0_WDV;
|
||||||
|
end else begin
|
||||||
|
NextWalkerState = LEVEL0;
|
||||||
|
PRegEn = 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
LEVEL0: begin
|
||||||
|
if (ValidPTE & LeafPTE & ~AccessAlert) begin
|
||||||
|
NextWalkerState = LEAF;
|
||||||
|
PageTableEntry = CurrentPTE;
|
||||||
|
PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00;
|
||||||
|
DTLBWriteM = DTLBMissMQ;
|
||||||
|
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
|
||||||
|
TranslationPAdr = {2'b00, TranslationVAdr[31:0]};
|
||||||
|
end else begin
|
||||||
|
NextWalkerState = FAULT;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
LEAF: begin
|
||||||
|
NextWalkerState = IDLE;
|
||||||
|
end
|
||||||
|
FAULT: begin
|
||||||
|
NextWalkerState = IDLE;
|
||||||
|
WalkerInstrPageFaultF = ~DTLBMissMQ;
|
||||||
|
WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore;
|
||||||
|
WalkerStorePageFaultM = DTLBMissMQ && MemStore;
|
||||||
|
end
|
||||||
|
|
||||||
|
// Default case should never happen, but is included for linter.
|
||||||
|
default: NextWalkerState = IDLE;
|
||||||
|
endcase
|
||||||
end
|
end
|
||||||
|
|
||||||
LEVEL0: begin
|
// A megapage is a Level 1 leaf page. This page must have zero PPN[0].
|
||||||
if (ValidPTE & LeafPTE & ~AccessAlert) begin
|
assign MegapageMisaligned = |(CurrentPPN[9:0]);
|
||||||
NextWalkerState = LEAF;
|
assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
|
||||||
PageTableEntry = CurrentPTE;
|
|
||||||
PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00;
|
|
||||||
DTLBWriteM = DTLBMissMQ;
|
|
||||||
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
|
|
||||||
TranslationPAdr = {2'b00, TranslationVAdrQ[31:0]};
|
|
||||||
end else begin
|
|
||||||
NextWalkerState = FAULT;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
LEAF: begin
|
assign VPN1 = TranslationVAdr[31:22];
|
||||||
|
assign VPN0 = TranslationVAdr[21:12];
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
// Capture page table entry from data cache
|
||||||
|
// *** may need to delay reading this value until the next clock cycle.
|
||||||
|
// The clk to q latency of the SRAM in the data cache will be long.
|
||||||
|
// I cannot see directly using this value. This is no different than
|
||||||
|
// a load delay hazard. This will require rewriting the walker fsm.
|
||||||
|
// also need a new signal to save. Should be a mealy output of the fsm
|
||||||
|
// request followed by ~stall.
|
||||||
|
flopenr #(32) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE);
|
||||||
|
//mux2 #(32) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE);
|
||||||
|
assign CurrentPTE = SavedPTE;
|
||||||
|
assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10];
|
||||||
|
|
||||||
|
// Assign outputs to ahblite
|
||||||
|
// *** Currently truncate address to 32 bits. This must be changed if
|
||||||
|
// we support larger physical address spaces
|
||||||
|
assign HPTWPAdrE = TranslationPAdr[31:0];
|
||||||
|
|
||||||
|
end else begin
|
||||||
|
|
||||||
|
logic [8:0] VPN3, VPN2, VPN1, VPN0;
|
||||||
|
|
||||||
|
logic TerapageMisaligned, GigapageMisaligned, BadTerapage, BadGigapage;
|
||||||
|
|
||||||
|
flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
|
||||||
|
|
||||||
|
/* -----\/----- EXCLUDED -----\/-----
|
||||||
|
assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV ||
|
||||||
|
WalkerState == LEVEL2_WDV || WalkerState == LEVEL3_WDV) && ~HPTWStall;
|
||||||
|
-----/\----- EXCLUDED -----/\----- */
|
||||||
|
|
||||||
|
//assign HPTWRead = (WalkerState == IDLE && HPTWTranslate) || WalkerState == LEVEL3 ||
|
||||||
|
// WalkerState == LEVEL2 || WalkerState == LEVEL1;
|
||||||
|
|
||||||
|
|
||||||
|
always_comb begin
|
||||||
|
PRegEn = 1'b0;
|
||||||
|
TranslationPAdr = '0;
|
||||||
|
HPTWReadE = 1'b0;
|
||||||
|
PageTableEntry = '0;
|
||||||
|
PageType = '0;
|
||||||
|
DTLBWriteM = '0;
|
||||||
|
ITLBWriteF = '0;
|
||||||
|
|
||||||
|
WalkerInstrPageFaultF = 1'b0;
|
||||||
|
WalkerLoadPageFaultM = 1'b0;
|
||||||
|
WalkerStorePageFaultM = 1'b0;
|
||||||
|
|
||||||
|
case (WalkerState)
|
||||||
|
IDLE: begin
|
||||||
|
if (HPTWTranslate && (SvMode == `SV48 || SvMode == `SV39)) begin
|
||||||
|
NextWalkerState = START;
|
||||||
|
end else begin
|
||||||
NextWalkerState = IDLE;
|
NextWalkerState = IDLE;
|
||||||
end
|
end
|
||||||
FAULT: begin
|
end
|
||||||
NextWalkerState = IDLE;
|
|
||||||
WalkerInstrPageFaultF = ~DTLBMissMQ;
|
|
||||||
WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore;
|
|
||||||
WalkerStorePageFaultM = DTLBMissMQ && MemStore;
|
|
||||||
end
|
|
||||||
|
|
||||||
// Default case should never happen, but is included for linter.
|
START: begin
|
||||||
default: NextWalkerState = IDLE;
|
if (HPTWTranslate && SvMode == `SV48) begin
|
||||||
endcase
|
NextWalkerState = LEVEL3_WDV;
|
||||||
end
|
|
||||||
|
|
||||||
// A megapage is a Level 1 leaf page. This page must have zero PPN[0].
|
|
||||||
assign MegapageMisaligned = |(CurrentPPN[9:0]);
|
|
||||||
assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
|
|
||||||
|
|
||||||
assign VPN1 = TranslationVAdrQ[31:22];
|
|
||||||
assign VPN0 = TranslationVAdrQ[21:12];
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
// Capture page table entry from data cache
|
|
||||||
// *** may need to delay reading this value until the next clock cycle.
|
|
||||||
// The clk to q latency of the SRAM in the data cache will be long.
|
|
||||||
// I cannot see directly using this value. This is no different than
|
|
||||||
// a load delay hazard. This will require rewriting the walker fsm.
|
|
||||||
// also need a new signal to save. Should be a mealy output of the fsm
|
|
||||||
// request followed by ~stall.
|
|
||||||
flopenr #(32) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE);
|
|
||||||
//mux2 #(32) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE);
|
|
||||||
assign CurrentPTE = SavedPTE;
|
|
||||||
assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10];
|
|
||||||
|
|
||||||
// Assign outputs to ahblite
|
|
||||||
// *** Currently truncate address to 32 bits. This must be changed if
|
|
||||||
// we support larger physical address spaces
|
|
||||||
assign HPTWPAdr = TranslationPAdr[31:0];
|
|
||||||
|
|
||||||
end else begin
|
|
||||||
|
|
||||||
logic [8:0] VPN3, VPN2, VPN1, VPN0;
|
|
||||||
|
|
||||||
logic TerapageMisaligned, GigapageMisaligned, BadTerapage, BadGigapage;
|
|
||||||
|
|
||||||
flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
|
|
||||||
|
|
||||||
/* -----\/----- EXCLUDED -----\/-----
|
|
||||||
assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV ||
|
|
||||||
WalkerState == LEVEL2_WDV || WalkerState == LEVEL3_WDV) && ~HPTWStall;
|
|
||||||
-----/\----- EXCLUDED -----/\----- */
|
|
||||||
|
|
||||||
//assign HPTWRead = (WalkerState == IDLE && HPTWTranslate) || WalkerState == LEVEL3 ||
|
|
||||||
// WalkerState == LEVEL2 || WalkerState == LEVEL1;
|
|
||||||
|
|
||||||
|
|
||||||
always_comb begin
|
|
||||||
PRegEn = 1'b0;
|
|
||||||
TranslationPAdr = '0;
|
|
||||||
HPTWRead = 1'b0;
|
|
||||||
PageTableEntry = '0;
|
|
||||||
PageType = '0;
|
|
||||||
DTLBWriteM = '0;
|
|
||||||
ITLBWriteF = '0;
|
|
||||||
|
|
||||||
WalkerInstrPageFaultF = 1'b0;
|
|
||||||
WalkerLoadPageFaultM = 1'b0;
|
|
||||||
WalkerStorePageFaultM = 1'b0;
|
|
||||||
|
|
||||||
case (WalkerState)
|
|
||||||
IDLE: begin
|
|
||||||
if (HPTWTranslate && (SvMode == `SV48 || SvMode == `SV39)) begin
|
|
||||||
NextWalkerState = START;
|
|
||||||
end else begin
|
|
||||||
NextWalkerState = IDLE;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
START: begin
|
|
||||||
if (HPTWTranslate && SvMode == `SV48) begin
|
|
||||||
NextWalkerState = LEVEL3_WDV;
|
|
||||||
TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000};
|
|
||||||
HPTWRead = 1'b1;
|
|
||||||
end else if (HPTWTranslate && SvMode == `SV39) begin
|
|
||||||
NextWalkerState = LEVEL2_WDV;
|
|
||||||
TranslationPAdr = {BasePageTablePPN, VPN2, 3'b000};
|
|
||||||
HPTWRead = 1'b1;
|
|
||||||
end else begin // *** should not get here
|
|
||||||
NextWalkerState = IDLE;
|
|
||||||
TranslationPAdr = '0;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
LEVEL3_WDV: begin
|
|
||||||
TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000};
|
TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000};
|
||||||
if (HPTWStall) begin
|
HPTWReadE = 1'b1;
|
||||||
NextWalkerState = LEVEL3_WDV;
|
end else if (HPTWTranslate && SvMode == `SV39) begin
|
||||||
end else begin
|
NextWalkerState = LEVEL2_WDV;
|
||||||
NextWalkerState = LEVEL3;
|
TranslationPAdr = {BasePageTablePPN, VPN2, 3'b000};
|
||||||
PRegEn = 1'b1;
|
HPTWReadE = 1'b1;
|
||||||
end
|
end else begin // *** should not get here
|
||||||
end
|
NextWalkerState = IDLE;
|
||||||
|
TranslationPAdr = '0;
|
||||||
LEVEL3: begin
|
|
||||||
// *** <FUTURE WORK> According to the architecture, we should
|
|
||||||
// fault upon finding a superpage that is misaligned or has 0
|
|
||||||
// access bit. The following commented line of code is
|
|
||||||
// supposed to perform that check. However, it is untested.
|
|
||||||
if (ValidPTE && LeafPTE && ~BadTerapage) begin
|
|
||||||
NextWalkerState = LEAF;
|
|
||||||
PageTableEntry = CurrentPTE;
|
|
||||||
PageType = (WalkerState == LEVEL3) ? 2'b11 : // *** not sure about this mux?
|
|
||||||
((WalkerState == LEVEL2) ? 2'b10 :
|
|
||||||
((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
|
|
||||||
DTLBWriteM = DTLBMissMQ;
|
|
||||||
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
|
|
||||||
TranslationPAdr = TranslationVAdrQ[`PA_BITS-1:0];
|
|
||||||
end
|
|
||||||
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
|
|
||||||
else if (ValidPTE && ~LeafPTE) begin
|
|
||||||
NextWalkerState = LEVEL2_WDV;
|
|
||||||
TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
|
|
||||||
HPTWRead = 1'b1;
|
|
||||||
end else begin
|
|
||||||
NextWalkerState = FAULT;
|
|
||||||
end
|
|
||||||
|
|
||||||
end
|
end
|
||||||
|
end
|
||||||
|
|
||||||
LEVEL2_WDV: begin
|
LEVEL3_WDV: begin
|
||||||
|
TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000};
|
||||||
|
HPTWReadE = 1'b1;
|
||||||
|
if (HPTWStall) begin
|
||||||
|
NextWalkerState = LEVEL3_WDV;
|
||||||
|
end else begin
|
||||||
|
NextWalkerState = LEVEL3;
|
||||||
|
PRegEn = 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
LEVEL3: begin
|
||||||
|
// *** <FUTURE WORK> According to the architecture, we should
|
||||||
|
// fault upon finding a superpage that is misaligned or has 0
|
||||||
|
// access bit. The following commented line of code is
|
||||||
|
// supposed to perform that check. However, it is untested.
|
||||||
|
if (ValidPTE && LeafPTE && ~BadTerapage) begin
|
||||||
|
NextWalkerState = LEAF;
|
||||||
|
PageTableEntry = CurrentPTE;
|
||||||
|
PageType = (WalkerState == LEVEL3) ? 2'b11 : // *** not sure about this mux?
|
||||||
|
((WalkerState == LEVEL2) ? 2'b10 :
|
||||||
|
((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
|
||||||
|
DTLBWriteM = DTLBMissMQ;
|
||||||
|
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
|
||||||
|
TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
|
||||||
|
end
|
||||||
|
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
|
||||||
|
else if (ValidPTE && ~LeafPTE) begin
|
||||||
|
NextWalkerState = LEVEL2_WDV;
|
||||||
TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
|
TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
|
||||||
//HPTWRead = 1'b1;
|
HPTWReadE = 1'b1;
|
||||||
if (HPTWStall) begin
|
end else begin
|
||||||
NextWalkerState = LEVEL2_WDV;
|
NextWalkerState = FAULT;
|
||||||
end else begin
|
|
||||||
NextWalkerState = LEVEL2;
|
|
||||||
PRegEn = 1'b1;
|
|
||||||
end
|
|
||||||
end
|
end
|
||||||
|
|
||||||
LEVEL2: begin
|
end
|
||||||
// *** <FUTURE WORK> According to the architecture, we should
|
|
||||||
// fault upon finding a superpage that is misaligned or has 0
|
|
||||||
// access bit. The following commented line of code is
|
|
||||||
// supposed to perform that check. However, it is untested.
|
|
||||||
if (ValidPTE && LeafPTE && ~BadGigapage) begin
|
|
||||||
NextWalkerState = LEAF;
|
|
||||||
PageTableEntry = CurrentPTE;
|
|
||||||
PageType = (WalkerState == LEVEL3) ? 2'b11 :
|
|
||||||
((WalkerState == LEVEL2) ? 2'b10 :
|
|
||||||
((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
|
|
||||||
DTLBWriteM = DTLBMissMQ;
|
|
||||||
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
|
|
||||||
TranslationPAdr = TranslationVAdrQ[`PA_BITS-1:0];
|
|
||||||
end
|
|
||||||
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
|
|
||||||
else if (ValidPTE && ~LeafPTE) begin
|
|
||||||
NextWalkerState = LEVEL1_WDV;
|
|
||||||
TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
|
|
||||||
HPTWRead = 1'b1;
|
|
||||||
end else begin
|
|
||||||
NextWalkerState = FAULT;
|
|
||||||
end
|
|
||||||
|
|
||||||
|
LEVEL2_WDV: begin
|
||||||
|
TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
|
||||||
|
HPTWReadE = 1'b1;
|
||||||
|
if (HPTWStall) begin
|
||||||
|
NextWalkerState = LEVEL2_WDV;
|
||||||
|
end else begin
|
||||||
|
NextWalkerState = LEVEL2;
|
||||||
|
PRegEn = 1'b1;
|
||||||
end
|
end
|
||||||
|
end
|
||||||
|
|
||||||
LEVEL1_WDV: begin
|
LEVEL2: begin
|
||||||
|
// *** <FUTURE WORK> According to the architecture, we should
|
||||||
|
// fault upon finding a superpage that is misaligned or has 0
|
||||||
|
// access bit. The following commented line of code is
|
||||||
|
// supposed to perform that check. However, it is untested.
|
||||||
|
if (ValidPTE && LeafPTE && ~BadGigapage) begin
|
||||||
|
NextWalkerState = LEAF;
|
||||||
|
PageTableEntry = CurrentPTE;
|
||||||
|
PageType = (WalkerState == LEVEL3) ? 2'b11 :
|
||||||
|
((WalkerState == LEVEL2) ? 2'b10 :
|
||||||
|
((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
|
||||||
|
DTLBWriteM = DTLBMissMQ;
|
||||||
|
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
|
||||||
|
TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
|
||||||
|
end
|
||||||
|
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
|
||||||
|
else if (ValidPTE && ~LeafPTE) begin
|
||||||
|
NextWalkerState = LEVEL1_WDV;
|
||||||
TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
|
TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
|
||||||
//HPTWRead = 1'b1;
|
HPTWReadE = 1'b1;
|
||||||
if (HPTWStall) begin
|
end else begin
|
||||||
NextWalkerState = LEVEL1_WDV;
|
NextWalkerState = FAULT;
|
||||||
end else begin
|
|
||||||
NextWalkerState = LEVEL1;
|
|
||||||
PRegEn = 1'b1;
|
|
||||||
end
|
|
||||||
end
|
end
|
||||||
|
|
||||||
LEVEL1: begin
|
end
|
||||||
// *** <FUTURE WORK> According to the architecture, we should
|
|
||||||
// fault upon finding a superpage that is misaligned or has 0
|
|
||||||
// access bit. The following commented line of code is
|
|
||||||
// supposed to perform that check. However, it is untested.
|
|
||||||
if (ValidPTE && LeafPTE && ~BadMegapage) begin
|
|
||||||
NextWalkerState = LEAF;
|
|
||||||
PageTableEntry = CurrentPTE;
|
|
||||||
PageType = (WalkerState == LEVEL3) ? 2'b11 :
|
|
||||||
((WalkerState == LEVEL2) ? 2'b10 :
|
|
||||||
((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
|
|
||||||
DTLBWriteM = DTLBMissMQ;
|
|
||||||
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
|
|
||||||
TranslationPAdr = TranslationVAdrQ[`PA_BITS-1:0];
|
|
||||||
|
|
||||||
end
|
LEVEL1_WDV: begin
|
||||||
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
|
TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
|
||||||
else if (ValidPTE && ~LeafPTE) begin
|
HPTWReadE = 1'b1;
|
||||||
NextWalkerState = LEVEL0_WDV;
|
if (HPTWStall) begin
|
||||||
TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
|
NextWalkerState = LEVEL1_WDV;
|
||||||
HPTWRead = 1'b1;
|
end else begin
|
||||||
end else begin
|
NextWalkerState = LEVEL1;
|
||||||
NextWalkerState = FAULT;
|
PRegEn = 1'b1;
|
||||||
end
|
|
||||||
end
|
end
|
||||||
|
end
|
||||||
|
|
||||||
LEVEL0_WDV: begin
|
LEVEL1: begin
|
||||||
|
// *** <FUTURE WORK> According to the architecture, we should
|
||||||
|
// fault upon finding a superpage that is misaligned or has 0
|
||||||
|
// access bit. The following commented line of code is
|
||||||
|
// supposed to perform that check. However, it is untested.
|
||||||
|
if (ValidPTE && LeafPTE && ~BadMegapage) begin
|
||||||
|
NextWalkerState = LEAF;
|
||||||
|
PageTableEntry = CurrentPTE;
|
||||||
|
PageType = (WalkerState == LEVEL3) ? 2'b11 :
|
||||||
|
((WalkerState == LEVEL2) ? 2'b10 :
|
||||||
|
((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
|
||||||
|
DTLBWriteM = DTLBMissMQ;
|
||||||
|
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
|
||||||
|
TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
|
||||||
|
|
||||||
|
end
|
||||||
|
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
|
||||||
|
else if (ValidPTE && ~LeafPTE) begin
|
||||||
|
NextWalkerState = LEVEL0_WDV;
|
||||||
TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
|
TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
|
||||||
if (HPTWStall) begin
|
HPTWReadE = 1'b1;
|
||||||
NextWalkerState = LEVEL0_WDV;
|
end else begin
|
||||||
end else begin
|
NextWalkerState = FAULT;
|
||||||
NextWalkerState = LEVEL0;
|
|
||||||
PRegEn = 1'b1;
|
|
||||||
end
|
|
||||||
end
|
end
|
||||||
|
end
|
||||||
|
|
||||||
LEVEL0: begin
|
LEVEL0_WDV: begin
|
||||||
if (ValidPTE && LeafPTE && ~AccessAlert) begin
|
TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
|
||||||
NextWalkerState = LEAF;
|
HPTWReadE = 1'b1;
|
||||||
PageTableEntry = CurrentPTE;
|
if (HPTWStall) begin
|
||||||
PageType = (WalkerState == LEVEL3) ? 2'b11 :
|
NextWalkerState = LEVEL0_WDV;
|
||||||
((WalkerState == LEVEL2) ? 2'b10 :
|
end else begin
|
||||||
((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
|
NextWalkerState = LEVEL0;
|
||||||
DTLBWriteM = DTLBMissMQ;
|
PRegEn = 1'b1;
|
||||||
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
|
|
||||||
TranslationPAdr = TranslationVAdrQ[`PA_BITS-1:0];
|
|
||||||
end else begin
|
|
||||||
NextWalkerState = FAULT;
|
|
||||||
end
|
|
||||||
end
|
end
|
||||||
|
end
|
||||||
|
|
||||||
LEAF: begin
|
LEVEL0: begin
|
||||||
NextWalkerState = IDLE;
|
if (ValidPTE && LeafPTE && ~AccessAlert) begin
|
||||||
|
NextWalkerState = LEAF;
|
||||||
|
PageTableEntry = CurrentPTE;
|
||||||
|
PageType = (WalkerState == LEVEL3) ? 2'b11 :
|
||||||
|
((WalkerState == LEVEL2) ? 2'b10 :
|
||||||
|
((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
|
||||||
|
DTLBWriteM = DTLBMissMQ;
|
||||||
|
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
|
||||||
|
TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
|
||||||
|
end else begin
|
||||||
|
NextWalkerState = FAULT;
|
||||||
end
|
end
|
||||||
|
end
|
||||||
|
|
||||||
FAULT: begin
|
LEAF: begin
|
||||||
NextWalkerState = IDLE;
|
NextWalkerState = IDLE;
|
||||||
WalkerInstrPageFaultF = ~DTLBMissMQ;
|
end
|
||||||
WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore;
|
|
||||||
WalkerStorePageFaultM = DTLBMissMQ && MemStore;
|
|
||||||
end
|
|
||||||
|
|
||||||
// Default case should never happen
|
FAULT: begin
|
||||||
default: begin
|
NextWalkerState = IDLE;
|
||||||
NextWalkerState = IDLE;
|
WalkerInstrPageFaultF = ~DTLBMissMQ;
|
||||||
end
|
WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore;
|
||||||
|
WalkerStorePageFaultM = DTLBMissMQ && MemStore;
|
||||||
|
end
|
||||||
|
|
||||||
endcase
|
// Default case should never happen
|
||||||
end
|
default: begin
|
||||||
|
NextWalkerState = IDLE;
|
||||||
|
end
|
||||||
|
|
||||||
// A terapage is a level 3 leaf page. This page must have zero PPN[2],
|
endcase
|
||||||
// zero PPN[1], and zero PPN[0]
|
|
||||||
assign TerapageMisaligned = |(CurrentPPN[26:0]);
|
|
||||||
// A gigapage is a Level 2 leaf page. This page must have zero PPN[1] and
|
|
||||||
// zero PPN[0]
|
|
||||||
assign GigapageMisaligned = |(CurrentPPN[17:0]);
|
|
||||||
// A megapage is a Level 1 leaf page. This page must have zero PPN[0].
|
|
||||||
assign MegapageMisaligned = |(CurrentPPN[8:0]);
|
|
||||||
|
|
||||||
assign BadTerapage = TerapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
|
|
||||||
assign BadGigapage = GigapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
|
|
||||||
assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
|
|
||||||
|
|
||||||
assign VPN3 = TranslationVAdrQ[47:39];
|
|
||||||
assign VPN2 = TranslationVAdrQ[38:30];
|
|
||||||
assign VPN1 = TranslationVAdrQ[29:21];
|
|
||||||
assign VPN0 = TranslationVAdrQ[20:12];
|
|
||||||
|
|
||||||
|
|
||||||
// Capture page table entry from ahblite
|
|
||||||
flopenr #(`XLEN) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE);
|
|
||||||
//mux2 #(`XLEN) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE);
|
|
||||||
assign CurrentPTE = SavedPTE;
|
|
||||||
assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10];
|
|
||||||
|
|
||||||
// Assign outputs to ahblite
|
|
||||||
// *** Currently truncate address to 32 bits. This must be changed if
|
|
||||||
// we support larger physical address spaces
|
|
||||||
assign HPTWPAdr = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]};
|
|
||||||
end
|
end
|
||||||
|
|
||||||
|
// A terapage is a level 3 leaf page. This page must have zero PPN[2],
|
||||||
|
// zero PPN[1], and zero PPN[0]
|
||||||
|
assign TerapageMisaligned = |(CurrentPPN[26:0]);
|
||||||
|
// A gigapage is a Level 2 leaf page. This page must have zero PPN[1] and
|
||||||
|
// zero PPN[0]
|
||||||
|
assign GigapageMisaligned = |(CurrentPPN[17:0]);
|
||||||
|
// A megapage is a Level 1 leaf page. This page must have zero PPN[0].
|
||||||
|
assign MegapageMisaligned = |(CurrentPPN[8:0]);
|
||||||
|
|
||||||
|
assign BadTerapage = TerapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
|
||||||
|
assign BadGigapage = GigapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
|
||||||
|
assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
|
||||||
|
|
||||||
|
assign VPN3 = TranslationVAdr[47:39];
|
||||||
|
assign VPN2 = TranslationVAdr[38:30];
|
||||||
|
assign VPN1 = TranslationVAdr[29:21];
|
||||||
|
assign VPN0 = TranslationVAdr[20:12];
|
||||||
|
|
||||||
|
|
||||||
|
// Capture page table entry from ahblite
|
||||||
|
flopenr #(`XLEN) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE);
|
||||||
|
//mux2 #(`XLEN) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE);
|
||||||
|
assign CurrentPTE = SavedPTE;
|
||||||
|
assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10];
|
||||||
|
|
||||||
|
// Assign outputs to ahblite
|
||||||
|
// *** Currently truncate address to 32 bits. This must be changed if
|
||||||
|
// we support larger physical address spaces
|
||||||
|
assign HPTWPAdrE = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]};
|
||||||
|
end
|
||||||
//endgenerate
|
//endgenerate
|
||||||
end else begin
|
end else begin
|
||||||
assign HPTWPAdr = 0;
|
assign HPTWPAdrE = 0;
|
||||||
assign HPTWTranslate = 0;
|
assign HPTWTranslate = 0;
|
||||||
assign HPTWRead = 0;
|
assign HPTWReadE = 0;
|
||||||
assign WalkerInstrPageFaultF = 0;
|
assign WalkerInstrPageFaultF = 0;
|
||||||
assign WalkerLoadPageFaultM = 0;
|
assign WalkerLoadPageFaultM = 0;
|
||||||
assign WalkerStorePageFaultM = 0;
|
assign WalkerStorePageFaultM = 0;
|
||||||
|
|||||||
@ -546,7 +546,7 @@ string tests32f[] = '{
|
|||||||
//if (`A_SUPPORTED) tests = {tests, tests64a};
|
//if (`A_SUPPORTED) tests = {tests, tests64a};
|
||||||
if (`F_SUPPORTED) tests = {tests64f, tests};
|
if (`F_SUPPORTED) tests = {tests64f, tests};
|
||||||
if (`D_SUPPORTED) tests = {tests64d, tests};
|
if (`D_SUPPORTED) tests = {tests64d, tests};
|
||||||
if (`MEM_VIRTMEM) tests = {tests64periph, tests64mmu, tests};
|
if (`MEM_VIRTMEM) tests = {tests64mmu, tests};
|
||||||
end
|
end
|
||||||
//tests = {tests64a, tests};
|
//tests = {tests64a, tests};
|
||||||
end else begin // RV32
|
end else begin // RV32
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user