Finally have the ptw correctly walking through the dcache to update the itlb.

Still not working fully.

wally-pipelined/regression/wave.do

@@ -3,48 +3,49 @@ quietly WaveActivateNextPane {} 0
 add wave -noupdate /testbench/clk
 add wave -noupdate /testbench/reset
 add wave -noupdate /testbench/memfilename
+add wave -noupdate /testbench/dut/hart/SATP_REGW
 add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
 add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
 add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
 add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
-add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM
+add wave -noupdate -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM
-add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM
+add wave -noupdate -group {Memory Stage} /testbench/dut/hart/PCM
-add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
+add wave -noupdate -group {Memory Stage} /testbench/InstrMName
-add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
+add wave -noupdate -group {Memory Stage} /testbench/dut/hart/InstrM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM
-add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
+add wave -noupdate -group HDU -expand -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
-add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
+add wave -noupdate -group HDU -expand -group interrupts /testbench/dut/hart/priv/trap/CommittedM
-add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
+add wave -noupdate -group HDU -expand -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
-add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
-add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
-add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
-add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
-add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
-add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
-add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
-add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
-add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
-add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
 add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
 add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
 add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
@@ -112,7 +113,7 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
 add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
 add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
 add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
-add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf
+add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rf
 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
@@ -155,12 +156,12 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/Write
 add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
 add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
 add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
-add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCNextF
+add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF
-add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF
+add wave -noupdate -group PCS /testbench/dut/hart/PCF
-add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD
+add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD
-add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE
+add wave -noupdate -group PCS /testbench/dut/hart/PCE
-add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM
+add wave -noupdate -group PCS /testbench/dut/hart/PCM
-add wave -noupdate -expand -group PCS /testbench/PCW
+add wave -noupdate -group PCS /testbench/PCW
 add wave -noupdate -group muldiv /testbench/dut/hart/mdu/InstrD
 add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcAE
 add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcBE
@@ -239,6 +240,12 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
 add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
 add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
 add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW
+add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrM
+add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrE
+add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/HPTWPAdrE
+add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/HPTWPAdrM
+add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrMtoDCache
+add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrEtoDCache
 add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/CurrState
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
@@ -271,18 +278,23 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cach
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
@@ -297,6 +309,9 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memo
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrOffsetM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrMaskedM
 add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Cacheable
 add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Idempotent
 add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/AtomicAllowed
@@ -306,6 +321,10 @@ add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PM
 add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF
 add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
 add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
+add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/SVMode
+add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
+add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
+add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
 add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss
 add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit
 add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress
@@ -351,26 +370,28 @@ add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME
 add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP
 add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM
 add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM
-add wave -noupdate -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState
+add wave -noupdate -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState
-add wave -noupdate -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall
+add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadM
-add wave -noupdate -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWRead
+add wave -noupdate -expand -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall
-add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF
+add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadPTE
-add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM
+add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE
-add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF
+add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF
-add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM
+add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM
-add wave -noupdate -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE
+add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF
-add wave -noupdate -group ptwalker -divider data
+add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM
-add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF
+add wave -noupdate -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE
-add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM
+add wave -noupdate -expand -group ptwalker -divider data
-add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF
+add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF
-add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM
+add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM
-add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM
+add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF
-add wave -noupdate -group {LSU ARB} -group lsu -color Gold /testbench/dut/hart/lsu/arbiter/CurrState
+add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM
-add wave -noupdate -group {LSU ARB} -group lsu -color {Medium Orchid} /testbench/dut/hart/lsu/arbiter/SelPTW
+add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM
-add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWTranslate
+add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/MemAdrM
-add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWRead
+add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/lsu/MemPAdrM
-add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWPAdr
+add wave -noupdate -expand -group {LSU ARB} -expand -group lsu -color Gold /testbench/dut/hart/lsu/arbiter/CurrState
-add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWReadPTE
+add wave -noupdate -expand -group {LSU ARB} -expand -group lsu -color {Medium Orchid} /testbench/dut/hart/lsu/arbiter/SelPTW
+add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWTranslate
+add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWReadPTE
 add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW
 add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HCLK
 add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESETn
@@ -395,13 +416,15 @@ add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genb
 add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/TXRDYb
 add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/RXRDYb
 add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
-add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HCLK
+add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HCLK
-add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HSELUART
+add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HSELUART
-add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HADDR
+add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HADDR
-add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HWRITE
+add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWRITE
-add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HWDATA
+add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWDATA
+add wave -noupdate /testbench/dut/hart/lsu/dcache/OFFSETLEN
+add wave -noupdate /testbench/dut/hart/lsu/dcache/INDEXLEN
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 12} {4076 ns} 0} {{Cursor 4} {8790617 ns} 0}
+WaveRestoreCursors {{Cursor 3} {21755 ns} 0} {{Cursor 4} {15501 ns} 0}
 quietly wave cursor active 1
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 297
@@ -417,4 +440,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {4026 ns} {4254 ns}
+WaveRestoreZoom {21597 ns} {21891 ns}

wally-pipelined/src/cache/dcache.sv

@@ -43,6 +43,7 @@ module dcache
 
    input logic [`XLEN-1:0]     WriteDataM,
    output logic [`XLEN-1:0]    ReadDataW,
+   output logic [`XLEN-1:0]    ReadDataM,   
    output logic 	       DCacheStall,
    output logic 	       CommittedM,
 
@@ -131,6 +132,7 @@ module dcache
   logic CntEn;
   logic CntReset;
   logic CPUBusy, PreviousCPUBusy;
+  logic SelEvict;
   
   
   typedef enum {STATE_READY,
@@ -297,16 +299,22 @@ module dcache
   // which means the CPU is ready to take data.  Or if the CPU just became
   // busy.  Then when we exit CPU_BUSY we want to ensure the data is not
   // updated, this is ~PreviousCPUBusy.
+  // also must update if cpu stalled and processing a read miss
+  // which occurs if in state miss read word delay.
   assign CPUBusy = CurrState == STATE_CPU_BUSY;
   flop #(1) CPUBusyReg(.clk, .d(CPUBusy), .q(PreviousCPUBusy));
   
-  assign ReadDataWEn = (~StallW & ~PreviousCPUBusy) | (NextState == STATE_CPU_BUSY & CurrState == STATE_READY);
+  assign ReadDataWEn = (~StallW & ~PreviousCPUBusy) | 
+		       (NextState == STATE_CPU_BUSY & CurrState == STATE_READY) |
+		       (CurrState == STATE_MISS_READ_WORD_DELAY);
   
   flopen #(`XLEN) ReadDataWReg(.clk(clk),
 			      .en(ReadDataWEn),
 			      .d(FinalReadDataWordM),
 			      .q(ReadDataW));
 
+  assign ReadDataM = FinalReadDataWordM;
+
   // write path
   subwordwrite subwordwrite(.HRDATA(ReadDataWordM),
 			    .HADDRD(MemPAdrM[2:0]),
@@ -340,7 +348,7 @@ module dcache
   // *** optimize this
   mux2 #(`PA_BITS) BaseAdrMux(.d0(MemPAdrM),
 			      .d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
-			      .s(AHBWrite & CacheableM),
+			      .s(SelEvict),
 			      .y(BasePAdrM));
 
   assign BasePAdrOffsetM = CacheableM ? {{OFFSETLEN}{1'b0}} : BasePAdrM[OFFSETLEN-1:0];
@@ -420,6 +428,7 @@ module dcache
     SelAMOWrite = 1'b0;
     CommittedM = 1'b0;        
     SelUncached = 1'b0;
+    SelEvict = 1'b0;
 
     case (CurrState)
       STATE_READY: begin
@@ -562,6 +571,7 @@ module dcache
 	AHBWrite = 1'b1;
 	SelAdrM = 1'b1;
 	CommittedM = 1'b1;
+	SelEvict = 1'b1;
 	if( FetchCountFlag & AHBAck) begin
 	  NextState = STATE_MISS_WRITE_CACHE_BLOCK;
 	end else begin

wally-pipelined/src/lsu/lsu.sv

@@ -129,9 +129,10 @@ module lsu
   logic [`XLEN-1:0] 	       HPTWReadPTE;
   logic 		       MMUReady;
   logic 		       HPTWStall;  
-  logic [`XLEN-1:0] 	       HPTWPAdr;
+  logic [`XLEN-1:0] 	       HPTWPAdrE;
+  logic [`XLEN-1:0] 	       HPTWPAdrM;  
   logic 		       HPTWTranslate;
-  logic 		       HPTWRead;
+  logic 		       HPTWReadM;
   logic [1:0] 		       MemRWMtoDCache;
   logic [2:0] 		       Funct3MtoDCache;
   logic [1:0] 		       AtomicMtoDCache;
@@ -146,6 +147,8 @@ module lsu
   logic 		       DCacheStall;
 
   logic 		       CacheableM;
+  logic 		       CacheableMtoDCache;
+  logic 		       SelPTW;
 
   logic 		       CommittedMfromDCache;
   logic 		       PendingInterruptMtoDCache;
@@ -169,9 +172,10 @@ module lsu
 				  .HPTWReadPTE(HPTWReadPTE),
 				  .MMUReady(HPTWReady),
 				  .HPTWStall(HPTWStall),
-				  .HPTWPAdr(HPTWPAdr),
+				  .HPTWPAdrE(HPTWPAdrE),
+				  .HPTWPAdrM(HPTWPAdrM),				  
 				  .HPTWTranslate(HPTWTranslate),
-				  .HPTWRead(HPTWRead),
+				  .HPTWReadM(HPTWReadM),
 				  .WalkerInstrPageFaultF(WalkerInstrPageFaultF),
 				  .WalkerLoadPageFaultM(WalkerLoadPageFaultM),  
 				  .WalkerStorePageFaultM(WalkerStorePageFaultM));
@@ -183,15 +187,17 @@ module lsu
 		 .reset(reset),
 		 // HPTW connection
 		 .HPTWTranslate(HPTWTranslate),
-		 .HPTWRead(HPTWRead),
+		 .HPTWReadM(HPTWReadM),
-		 .HPTWPAdr(HPTWPAdr),
+		 .HPTWPAdrE(HPTWPAdrE),
-		 .HPTWReadPTE(HPTWReadPTE),
+		 .HPTWPAdrM(HPTWPAdrM),		 
+		 //.HPTWReadPTE(HPTWReadPTE),
 		 .HPTWStall(HPTWStall),		 
 		 // CPU connection
 		 .MemRWM(MemRWM),
 		 .Funct3M(Funct3M),
 		 .AtomicM(AtomicM),
 		 .MemAdrM(MemAdrM),
+		 .MemAdrE(MemAdrE),		 
 		 .CommittedM(CommittedM),
 		 .PendingInterruptM(PendingInterruptM),		
 		 .StallW(StallW),
@@ -205,13 +211,15 @@ module lsu
 		 .Funct3MtoDCache(Funct3MtoDCache),
 		 .AtomicMtoDCache(AtomicMtoDCache),
 		 .MemAdrMtoDCache(MemAdrMtoDCache),
+		 .MemAdrEtoDCache(MemAdrEtoDCache),
 		 .StallWtoDCache(StallWtoDCache),
 		 .SquashSCWfromDCache(SquashSCWfromDCache),      
 		 .DataMisalignedMfromDCache(DataMisalignedMfromDCache),
 		 .ReadDataWfromDCache(ReadDataWfromDCache),
 		 .CommittedMfromDCache(CommittedMfromDCache),
 		 .PendingInterruptMtoDCache(PendingInterruptMtoDCache),
-		 .DCacheStall(DCacheStall));
+		 .DCacheStall(DCacheStall),
+		 .SelPTW(SelPTW));
     
   
   mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
@@ -239,10 +247,10 @@ module lsu
        //       .SelRegions(DHSELRegionsM),
        .*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist?
 
-
+  assign CacheableMtoDCache = SelPTW ? 1'b1 : CacheableM;
   generate
-    if (`XLEN == 32) assign DCtoAHBSizeM = CacheableM ? 3'b010 : Funct3MtoDCache;
+    if (`XLEN == 32) assign DCtoAHBSizeM = CacheableMtoDCache ? 3'b010 : Funct3MtoDCache;
-    else assign DCtoAHBSizeM = CacheableM ? 3'b011 : Funct3MtoDCache;
+    else assign DCtoAHBSizeM = CacheableMtoDCache ? 3'b011 : Funct3MtoDCache;
   endgenerate;
 
 
@@ -309,30 +317,27 @@ module lsu
   assign LoadMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoDCache[1];
   assign StoreMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoDCache[0];
 
-  // *** BUG
-  assign MemAdrEtoDCache = MemAdrE; // needs to be muxed in lsuarb.
-  
-
   dcache dcache(.clk(clk),
 		.reset(reset),
 		.StallM(StallM),
-		.StallW(StallW),
+		.StallW(StallWtoDCache),
 		.FlushM(FlushM),
-		.FlushW(FlushW),
+		.FlushW(FlushWtoDCache),
 		.MemRWM(MemRWMtoDCache),
 		.Funct3M(Funct3MtoDCache),
 		.Funct7M(Funct7M),		
 		.AtomicM(AtomicMtoDCache),
-		.MemAdrE(MemAdrEtoDCache),  // *** add to arb
+		.MemAdrE(MemAdrEtoDCache),
 		.MemPAdrM(MemPAdrM),
 		.WriteDataM(WriteDataM),
 		.ReadDataW(ReadDataWfromDCache),
+		.ReadDataM(HPTWReadPTE),
 		.DCacheStall(DCacheStall),
 		.CommittedM(CommittedMfromDCache),
 		.ExceptionM(ExceptionM),
 		.PendingInterruptM(PendingInterruptMtoDCache),		
 		.DTLBMissM(DTLBMissM),
-		.CacheableM(CacheableM), 
+		.CacheableM(CacheableMtoDCache), 
 		.DTLBWriteM(DTLBWriteM),
 
 		// AHB connection

wally-pipelined/src/lsu/lsuArb.sv

@@ -31,10 +31,11 @@ module lsuArb
 
    // from page table walker
    input logic 		    HPTWTranslate,
-   input logic 		    HPTWRead,
+   input logic 		    HPTWReadM,
-   input logic [`XLEN-1:0]  HPTWPAdr,
+   input logic [`XLEN-1:0]  HPTWPAdrE,
+   input logic [`XLEN-1:0]  HPTWPAdrM, 
    // to page table walker.
-   output logic [`XLEN-1:0] HPTWReadPTE,
+   //output logic [`XLEN-1:0] HPTWReadPTE,
    output logic 	    HPTWStall, 
 
    // from CPU
@@ -42,6 +43,7 @@ module lsuArb
    input logic [2:0] 	    Funct3M,
    input logic [1:0] 	    AtomicM,
    input logic [`XLEN-1:0]  MemAdrM,
+   input logic [`XLEN-1:0]  MemAdrE,
    input logic 		    StallW,
    input logic 		    PendingInterruptM,
    // to CPU
@@ -57,8 +59,11 @@ module lsuArb
    output logic [2:0] 	    Funct3MtoDCache,
    output logic [1:0] 	    AtomicMtoDCache,
    output logic [`XLEN-1:0] MemAdrMtoDCache,
+   output logic [`XLEN-1:0] MemAdrEtoDCache, 
    output logic 	    StallWtoDCache,
    output logic 	    PendingInterruptMtoDCache,
+   output logic 	    SelPTW,
+   
 
    // from D Cache
    input logic 		    CommittedMfromDCache,
@@ -86,7 +91,6 @@ module lsuArb
   
 
   statetype CurrState, NextState;
-  logic 		    SelPTW;
   logic [2:0] PTWSize;
   
 
@@ -136,7 +140,7 @@ module lsuArb
   // multiplex the outputs to LSU
   assign DisableTranslation = SelPTW;  // change names between SelPTW would be confusing in DTLB.
   assign SelPTW = (CurrState == StatePTWActive && HPTWTranslate) || (CurrState == StateReady && HPTWTranslate);
-  assign MemRWMtoDCache = SelPTW ? {HPTWRead, 1'b0} : MemRWM;
+  assign MemRWMtoDCache = SelPTW ? {HPTWReadM, 1'b0} : MemRWM;
   
   generate
     assign PTWSize = (`XLEN==32 ? 3'b010 : 3'b011); // 32 or 64-bit access from htpw
@@ -144,7 +148,8 @@ module lsuArb
   mux2 #(3) sizemux(Funct3M, PTWSize, SelPTW, Funct3MtoDCache);
 
   assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM;
-  assign MemAdrMtoDCache = SelPTW ? HPTWPAdr : MemAdrM;
+  assign MemAdrMtoDCache = SelPTW ? HPTWPAdrM : MemAdrM;
+  assign MemAdrEtoDCache = SelPTW ? HPTWPAdrE : MemAdrE;  
   assign StallWtoDCache = SelPTW ? 1'b0 : StallW;
   // always block interrupts when using the hardware page table walker.
   assign CommittedM = SelPTW ? 1'b1 : CommittedMfromDCache;
@@ -152,7 +157,7 @@ module lsuArb
   // demux the inputs from LSU to walker or cpu's data port.
 
   assign ReadDataW = SelPTW ? `XLEN'b0 : ReadDataWfromDCache;  // probably can avoid this demux
-  assign HPTWReadPTE = SelPTW ? ReadDataWfromDCache : `XLEN'b0 ;  // probably can avoid this demux
+  //assign HPTWReadPTE = SelPTW ? ReadDataWfromDCache : `XLEN'b0 ;  // probably can avoid this demux
   assign SquashSCW = SelPTW ? 1'b0 : SquashSCWfromDCache;
   assign DataMisalignedM = SelPTW ? 1'b0 : DataMisalignedMfromDCache;
   // *** need to rename DcacheStall and Datastall.

wally-pipelined/src/mmu/pagetablewalker.sv

@@ -59,9 +59,10 @@ module pagetablewalker
    input logic 		    HPTWStall,
 
    // *** modify to send to LSU
-   output logic [`XLEN-1:0] HPTWPAdr, // this probalby should be `PA_BITS wide
+   output logic [`XLEN-1:0] HPTWPAdrE, // this probalby should be `PA_BITS wide
+   output logic [`XLEN-1:0] HPTWPAdrM, // this probalby should be `PA_BITS wide   
    output logic 	    HPTWTranslate, // *** rename to HPTWReq
-   output logic 	    HPTWRead,
+   output logic 	    HPTWReadM,
 
 
    // Faults
@@ -70,6 +71,8 @@ module pagetablewalker
    output logic 	    WalkerStorePageFaultM
    );
 
+  logic 		    HPTWReadE;
+
   generate
     if (`MEM_VIRTMEM) begin
       // Internal signals
@@ -116,6 +119,15 @@ module pagetablewalker
       logic 			    SelDataTranslation;
       
       
+	flop #(`XLEN) HPTWPAdrMReg(.clk(clk),
+				   .d(HPTWPAdrE),
+				   .q(HPTWPAdrM));
+
+	flop #(1) HPTWReadMReg(.clk(clk),
+			       .d(HPTWReadE),
+			       .q(HPTWReadM));
+
+
       assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
 
       assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0];
@@ -177,7 +189,7 @@ module pagetablewalker
       assign PageTypeM = PageType;
 
 
-//      generate
+      //      generate
       if (`XLEN == 32) begin
         logic [9:0] VPN1, VPN0;
 
@@ -191,7 +203,7 @@ module pagetablewalker
         always_comb begin
 	  PRegEn = 1'b0;
 	  TranslationPAdr = '0;
-      HPTWRead = 1'b0;
+	  HPTWReadE = 1'b0;
           PageTableEntry = '0;
           PageType = '0;
           DTLBWriteM = '0;
@@ -213,11 +225,12 @@ module pagetablewalker
             START: begin
               NextWalkerState = LEVEL1_WDV;
               TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00};
-          HPTWRead = 1'b1;
+              HPTWReadE = 1'b1;
             end
             
             LEVEL1_WDV: begin
               TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00};
+              HPTWReadE = 1'b1;
               if (HPTWStall) begin
                 NextWalkerState = LEVEL1_WDV;
               end else begin
@@ -237,13 +250,13 @@ module pagetablewalker
                 PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00;  // *** not sure about this mux?
                 DTLBWriteM = DTLBMissMQ;
                 ITLBWriteF = ~DTLBMissMQ;  // Prefer data over instructions
-                  TranslationPAdr = {2'b00, TranslationVAdrQ[31:0]};
+                TranslationPAdr = {2'b00, TranslationVAdr[31:0]};
               end
               // else if (ValidPTE && LeafPTE)    NextWalkerState = LEAF;  // *** Once the above line is properly tested, delete this line.
               else if (ValidPTE && ~LeafPTE) begin
 		NextWalkerState = LEVEL0_WDV;
                 TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
-            HPTWRead = 1'b1;
+		HPTWReadE = 1'b1;
               end else begin
                 NextWalkerState = FAULT;
               end
@@ -251,6 +264,7 @@ module pagetablewalker
             
             LEVEL0_WDV: begin
               TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
+              HPTWReadE = 1'b1;
               if (HPTWStall) begin 
 		NextWalkerState = LEVEL0_WDV;
               end else begin 
@@ -266,7 +280,7 @@ module pagetablewalker
                 PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00;
                 DTLBWriteM = DTLBMissMQ;
                 ITLBWriteF = ~DTLBMissMQ;  // Prefer data over instructions
-                  TranslationPAdr = {2'b00, TranslationVAdrQ[31:0]};
+                TranslationPAdr = {2'b00, TranslationVAdr[31:0]};
               end else begin
                 NextWalkerState = FAULT;
               end
@@ -291,8 +305,8 @@ module pagetablewalker
         assign MegapageMisaligned = |(CurrentPPN[9:0]);
         assign BadMegapage = MegapageMisaligned || AccessAlert;  // *** Implement better access/dirty scheme
 
-          assign VPN1 = TranslationVAdrQ[31:22];
+        assign VPN1 = TranslationVAdr[31:22];
-          assign VPN0 = TranslationVAdrQ[21:12];
+        assign VPN0 = TranslationVAdr[21:12];
 
         
 
@@ -311,7 +325,7 @@ module pagetablewalker
         // Assign outputs to ahblite
         // *** Currently truncate address to 32 bits. This must be changed if
         // we support larger physical address spaces
-          assign HPTWPAdr = TranslationPAdr[31:0];
+        assign HPTWPAdrE = TranslationPAdr[31:0];
 
       end else begin
         
@@ -333,7 +347,7 @@ module pagetablewalker
         always_comb begin
 	  PRegEn = 1'b0;
 	  TranslationPAdr = '0;
-      HPTWRead = 1'b0;
+	  HPTWReadE = 1'b0;
           PageTableEntry = '0;
           PageType = '0;
           DTLBWriteM = '0;
@@ -356,11 +370,11 @@ module pagetablewalker
               if (HPTWTranslate && SvMode == `SV48) begin
 		NextWalkerState = LEVEL3_WDV;
                 TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000};
-            HPTWRead = 1'b1;
+		HPTWReadE = 1'b1;
               end else if (HPTWTranslate && SvMode == `SV39) begin
 		NextWalkerState = LEVEL2_WDV;
                 TranslationPAdr = {BasePageTablePPN, VPN2, 3'b000};
-            HPTWRead = 1'b1;
+		HPTWReadE = 1'b1;
               end else begin // *** should not get here
                 NextWalkerState = IDLE;
 		TranslationPAdr = '0;
@@ -369,6 +383,7 @@ module pagetablewalker
 
             LEVEL3_WDV: begin
               TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000};
+              HPTWReadE = 1'b1;
               if (HPTWStall) begin
 		NextWalkerState = LEVEL3_WDV;
               end else begin
@@ -390,13 +405,13 @@ module pagetablewalker
                             ((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
                 DTLBWriteM = DTLBMissMQ;
                 ITLBWriteF = ~DTLBMissMQ;  // Prefer data over instructions
-                  TranslationPAdr = TranslationVAdrQ[`PA_BITS-1:0];
+                TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
               end 
               // else if (ValidPTE && LeafPTE)    NextWalkerState = LEAF;  // *** Once the above line is properly tested, delete this line.
               else if (ValidPTE && ~LeafPTE) begin
                 NextWalkerState = LEVEL2_WDV;
                 TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
-                  HPTWRead = 1'b1;
+                HPTWReadE = 1'b1;
               end else begin
                 NextWalkerState = FAULT;
               end
@@ -405,7 +420,7 @@ module pagetablewalker
 
             LEVEL2_WDV:  begin
               TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
-                //HPTWRead = 1'b1;
+              HPTWReadE = 1'b1;
               if (HPTWStall) begin
                 NextWalkerState = LEVEL2_WDV;
               end else begin
@@ -427,13 +442,13 @@ module pagetablewalker
                             ((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
                 DTLBWriteM = DTLBMissMQ;
                 ITLBWriteF = ~DTLBMissMQ;  // Prefer data over instructions
-                  TranslationPAdr = TranslationVAdrQ[`PA_BITS-1:0];
+                TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
               end
               // else if (ValidPTE && LeafPTE)    NextWalkerState = LEAF;  // *** Once the above line is properly tested, delete this line.
               else if (ValidPTE && ~LeafPTE) begin
                 NextWalkerState = LEVEL1_WDV;
                 TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
-                  HPTWRead = 1'b1;
+                HPTWReadE = 1'b1;
               end else begin
                 NextWalkerState = FAULT;
               end
@@ -442,7 +457,7 @@ module pagetablewalker
 
             LEVEL1_WDV: begin
               TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
-                //HPTWRead = 1'b1;
+              HPTWReadE = 1'b1;
               if (HPTWStall) begin 
                 NextWalkerState = LEVEL1_WDV;
               end else begin
@@ -464,14 +479,14 @@ module pagetablewalker
                             ((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
                 DTLBWriteM = DTLBMissMQ;
                 ITLBWriteF = ~DTLBMissMQ;  // Prefer data over instructions
-                  TranslationPAdr = TranslationVAdrQ[`PA_BITS-1:0];
+                TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
                 
               end
               // else if (ValidPTE && LeafPTE)    NextWalkerState = LEAF;  // *** Once the above line is properly tested, delete this line.
               else if (ValidPTE && ~LeafPTE) begin
                 NextWalkerState = LEVEL0_WDV;
                 TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
-                  HPTWRead = 1'b1;
+                HPTWReadE = 1'b1;
               end else begin 
                 NextWalkerState = FAULT;
               end
@@ -479,6 +494,7 @@ module pagetablewalker
 
             LEVEL0_WDV: begin
               TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
+              HPTWReadE = 1'b1;
               if (HPTWStall) begin 
                 NextWalkerState = LEVEL0_WDV;
               end else begin
@@ -496,7 +512,7 @@ module pagetablewalker
                             ((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
                 DTLBWriteM = DTLBMissMQ;
                 ITLBWriteF = ~DTLBMissMQ;  // Prefer data over instructions
-                  TranslationPAdr = TranslationVAdrQ[`PA_BITS-1:0];
+                TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
               end else begin 
                 NextWalkerState = FAULT;
               end
@@ -534,10 +550,10 @@ module pagetablewalker
         assign BadGigapage = GigapageMisaligned || AccessAlert;  // *** Implement better access/dirty scheme
         assign BadMegapage = MegapageMisaligned || AccessAlert;  // *** Implement better access/dirty scheme
 
-          assign VPN3 = TranslationVAdrQ[47:39];
+        assign VPN3 = TranslationVAdr[47:39];
-          assign VPN2 = TranslationVAdrQ[38:30];
+        assign VPN2 = TranslationVAdr[38:30];
-          assign VPN1 = TranslationVAdrQ[29:21];
+        assign VPN1 = TranslationVAdr[29:21];
-          assign VPN0 = TranslationVAdrQ[20:12];
+        assign VPN0 = TranslationVAdr[20:12];
 
 
         // Capture page table entry from ahblite
@@ -549,13 +565,13 @@ module pagetablewalker
         // Assign outputs to ahblite
         // *** Currently truncate address to 32 bits. This must be changed if
         // we support larger physical address spaces
-          assign HPTWPAdr = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]};
+        assign HPTWPAdrE = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]};
       end
       //endgenerate
     end else begin
-      assign HPTWPAdr = 0;
+      assign HPTWPAdrE = 0;
       assign HPTWTranslate = 0;
-      assign HPTWRead = 0;
+      assign HPTWReadE = 0;
       assign WalkerInstrPageFaultF = 0;
       assign WalkerLoadPageFaultM = 0;
       assign WalkerStorePageFaultM = 0;

wally-pipelined/testbench/testbench-imperas.sv

@@ -546,7 +546,7 @@ string tests32f[] = '{
         //if (`A_SUPPORTED) tests = {tests, tests64a};
         if (`F_SUPPORTED) tests = {tests64f, tests};
         if (`D_SUPPORTED) tests = {tests64d, tests};
-        if (`MEM_VIRTMEM) tests = {tests64periph, tests64mmu, tests};
+        if (`MEM_VIRTMEM) tests = {tests64mmu, tests};
       end
       //tests = {tests64a, tests};
     end else begin // RV32