diff --git a/.gitmodules b/.gitmodules index 54ed892d3..1dc9e38aa 100644 --- a/.gitmodules +++ b/.gitmodules @@ -31,3 +31,6 @@ [submodule "cvw-arch-verif"] path = addins/cvw-arch-verif url = https://github.com/openhwgroup/cvw-arch-verif +[submodule "addins/riscvISACOV"] + path = addins/riscvISACOV + url = https://github.com/riscv-verification/riscvISACOV.git diff --git a/addins/cvw-arch-verif b/addins/cvw-arch-verif index 07679a317..9d54f3f8e 160000 --- a/addins/cvw-arch-verif +++ b/addins/cvw-arch-verif @@ -1 +1 @@ -Subproject commit 07679a31750eb1054055afff0d42f467c5e87727 +Subproject commit 9d54f3f8e902bb85db74305993d2fc03796b57bc diff --git a/addins/riscvISACOV b/addins/riscvISACOV new file mode 160000 index 000000000..ac9fa2d38 --- /dev/null +++ b/addins/riscvISACOV @@ -0,0 +1 @@ +Subproject commit ac9fa2d386c0cb2f44e1e1e83a555d585034dfa3 diff --git a/bin/extractFunctionRadix.sh b/bin/extractFunctionRadix.sh index 42e3db0b2..a0480f855 100755 --- a/bin/extractFunctionRadix.sh +++ b/bin/extractFunctionRadix.sh @@ -3,7 +3,7 @@ ###################### ## extractFunctionRadix.sh ## -## Written: Ross Thompson +## Written: Rose Thompson ## email: ross1728@gmail.com ## Created: March 1, 2021 ## Modified: March 10, 2021 diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index c5dd0fbd3..88600ba26 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -2,7 +2,7 @@ ########################################### ## Tool chain install script. ## -## Written: Ross Thompson ross1728@gmail.com +## Written: Rose Thompson ross1728@gmail.com ## Created: 18 January 2023 ## Modified: 22 January 2023 ## Modified: 23 March 2023 diff --git a/bin/wsim b/bin/wsim index cef7eca27..9867f7524 100755 --- a/bin/wsim +++ b/bin/wsim @@ -106,6 +106,9 @@ else: suffix = "" flags = suffix + " " + ImperasPlusArgs +if((args.lockstep or args.fcov) and args.sim == "questa"): + prefix = "MTI_VCO_MODE=64 " + prefix + # other flags if (args.ccov): flags += " --ccov" diff --git a/fpga/comport.setup b/fpga/comport.setup index cb4108b56..462d0be99 100644 --- a/fpga/comport.setup +++ b/fpga/comport.setup @@ -1,3 +1,3 @@ -sudo chown ross:ross /dev/ttyUSB1 +sudo chown rose:rose /dev/ttyUSB1 stty -F /dev/ttyUSB1 57600 cs8 -cstopb -parenb cat /dev/ttyUSB1 diff --git a/fpga/constraints/constraints-ArtyA7.xdc b/fpga/constraints/constraints-ArtyA7.xdc index 4dadf3987..7eb3598f5 100644 --- a/fpga/constraints/constraints-ArtyA7.xdc +++ b/fpga/constraints/constraints-ArtyA7.xdc @@ -7,34 +7,34 @@ create_generated_clock -name SPISDCClock -source [get_pins clk_out3_xlnx_mmcm] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncore.uncore/sdc.sdc/SPICLK] ##### clock ##### -set_property PACKAGE_PIN E3 [get_ports {default_100mhz_clk}] -set_property IOSTANDARD LVCMOS33 [get_ports {default_100mhz_clk}] +set_property PACKAGE_PIN E3 [get_ports default_100mhz_clk] +set_property IOSTANDARD LVCMOS33 [get_ports default_100mhz_clk] ##### RVVI Ethernet #### # taken from https://github.com/alexforencich/verilog-ethernet/blob/master/example/Arty/fpga/fpga.xdc -set_property -dict {LOC F15 IOSTANDARD LVCMOS33} [get_ports phy_rx_clk] -set_property -dict {LOC D18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[0]}] -set_property -dict {LOC E17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[1]}] -set_property -dict {LOC E18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[2]}] -set_property -dict {LOC G17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[3]}] -set_property -dict {LOC G16 IOSTANDARD LVCMOS33} [get_ports phy_rx_dv] -set_property -dict {LOC C17 IOSTANDARD LVCMOS33} [get_ports phy_rx_er] -set_property -dict {LOC H16 IOSTANDARD LVCMOS33} [get_ports phy_tx_clk] -set_property -dict {LOC H14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[0]}] -set_property -dict {LOC J14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[1]}] -set_property -dict {LOC J13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[2]}] -set_property -dict {LOC H17 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[3]}] -set_property -dict {LOC H15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports phy_tx_en] -set_property -dict {LOC D17 IOSTANDARD LVCMOS33} [get_ports phy_col] -set_property -dict {LOC G14 IOSTANDARD LVCMOS33} [get_ports phy_crs] -set_property -dict {LOC G18 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_ref_clk] -set_property -dict {LOC C16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_reset_n] +set_property -dict {LOC F15 IOSTANDARD LVCMOS33} [get_ports phy_rx_clk] +set_property -dict {LOC D18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[0]}] +set_property -dict {LOC E17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[1]}] +set_property -dict {LOC E18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[2]}] +set_property -dict {LOC G17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[3]}] +set_property -dict {LOC G16 IOSTANDARD LVCMOS33} [get_ports phy_rx_dv] +set_property -dict {LOC C17 IOSTANDARD LVCMOS33} [get_ports phy_rx_er] +set_property -dict {LOC H16 IOSTANDARD LVCMOS33} [get_ports phy_tx_clk] +set_property -dict {LOC H14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[0]}] +set_property -dict {LOC J14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[1]}] +set_property -dict {LOC J13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[2]}] +set_property -dict {LOC H17 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[3]}] +set_property -dict {LOC H15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports phy_tx_en] +set_property -dict {LOC D17 IOSTANDARD LVCMOS33} [get_ports phy_col] +set_property -dict {LOC G14 IOSTANDARD LVCMOS33} [get_ports phy_crs] +set_property -dict {LOC G18 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_ref_clk] +set_property -dict {LOC C16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_reset_n] create_clock -period 40.000 -name phy_rx_clk [get_ports phy_rx_clk] create_clock -period 40.000 -name phy_tx_clk [get_ports phy_tx_clk] set_false_path -to [get_ports {phy_ref_clk phy_reset_n}] -set_output_delay 0 [get_ports {phy_ref_clk phy_reset_n}] +set_output_delay 0.000 [get_ports {phy_ref_clk phy_reset_n}] ##### GPI #### set_property PACKAGE_PIN A8 [get_ports {GPI[0]}] @@ -87,16 +87,16 @@ set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [ge set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports resetn] set_max_delay -from [get_ports resetn] 20.000 set_false_path -from [get_ports resetn] -set_property PACKAGE_PIN C2 [get_ports {resetn}] -set_property IOSTANDARD LVCMOS33 [get_ports {resetn}] +set_property PACKAGE_PIN C2 [get_ports resetn] +set_property IOSTANDARD LVCMOS33 [get_ports resetn] set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [get_ports south_reset] set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports south_reset] set_max_delay -from [get_ports south_reset] 20.000 set_false_path -from [get_ports south_reset] -set_property PACKAGE_PIN D9 [get_ports {south_reset}] -set_property IOSTANDARD LVCMOS33 [get_ports {south_reset}] +set_property PACKAGE_PIN D9 [get_ports south_reset] +set_property IOSTANDARD LVCMOS33 [get_ports south_reset] @@ -125,15 +125,27 @@ set_property IOSTANDARD LVCMOS33 [get_ports {south_reset}] #set_property PULLUP true [get_ports {SDCCD}] # SDCDat[3] -set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCS}] +set_property PACKAGE_PIN D4 [get_ports SDCCS] +set_property IOSTANDARD LVCMOS33 [get_ports SDCCS] +set_property PULLTYPE PULLUP [get_ports SDCCS] # set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[2]}] # set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[1]}] # SDCDat[0] -set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCIn}] -set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCLK}] -set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCmd}] -set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCD}] -set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCWP}] +set_property PACKAGE_PIN F4 [get_ports SDCIn] +set_property IOSTANDARD LVCMOS33 [get_ports SDCIn] +set_property PULLTYPE PULLUP [get_ports SDCIn] +set_property PACKAGE_PIN F3 [get_ports SDCCLK] +set_property IOSTANDARD LVCMOS33 [get_ports SDCCLK] +set_property PULLTYPE PULLUP [get_ports SDCCLK] +set_property PACKAGE_PIN D3 [get_ports SDCCmd] +set_property IOSTANDARD LVCMOS33 [get_ports SDCCmd] +set_property PULLTYPE PULLUP [get_ports SDCCmd] +set_property PACKAGE_PIN H2 [get_ports SDCCD] +set_property IOSTANDARD LVCMOS33 [get_ports SDCCD] +set_property PULLTYPE PULLUP [get_ports SDCCD] +set_property PACKAGE_PIN G2 [get_ports SDCWP] +set_property IOSTANDARD LVCMOS33 [get_ports SDCWP] +set_property PULLTYPE PULLUP [get_ports SDCWP] set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCCS}] @@ -158,54 +170,54 @@ set_max_delay -datapath_only -from [get_pins xlnx_ddr3_c0/u_xlnx_ddr3_mig/u_memc # ddr3 -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[0]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[1]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[2]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[3]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[4]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[5]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[6]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[7]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[8]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[9]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[10]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[11]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[12]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[13]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[14]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[15]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[0]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[1]] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[0]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[1]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[2]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[3]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[4]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[5]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[6]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[7]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[8]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[9]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[10]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[11]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[12]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[13]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[14]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[15]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[0]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[1]}] set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[0]] set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[0]] set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[1]] set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[1]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[13]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[12]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[11]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[10]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[9]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[8]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[7]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[6]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[5]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[4]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[3]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[2]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[1]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[0]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[2]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[1]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[0]] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[13]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[12]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[11]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[10]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[9]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[8]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[7]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[6]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[5]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[4]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[3]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[2]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[1]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[0]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[2]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[1]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[0]}] set_property IOSTANDARD DIFF [get_ports ddr3_ck_p[0]] set_property IOSTANDARD DIFF [get_ports ddr3_ck_n[0]] set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n] set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n] set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n] set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n] -set_property IOSTANDARD SSTL135 [get_ports ddr3_cke[0]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_odt[0]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_cs_n[0]] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_cke[0]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_odt[0]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_cs_n[0]}] set_properity PACKAGE_PIN K5 [get_ports ddr3_dq[0]] @@ -257,3 +269,28 @@ set_properity PACKAGE_PIN N5 [get_ports ddr3_cke[0]] set_properity PACKAGE_PIN R5 [get_ports ddr3_odt[0]] set_properity PACKAGE_PIN U8 [get_ports ddr3_cs_n[0]] + +create_clock -period 40.000 -name VIRTUAL_clk_out3_mmcm -waveform {0.000 20.000} +set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports {GPI[*]}] +set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports {GPI[*]}] +set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCCD] +set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCD] +set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCIn] +set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCIn] +set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCWP] +set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCWP] +set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports UARTSin] +set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports UARTSin] +create_clock -period 12.000 -name VIRTUAL_clk_pll_i -waveform {0.000 6.000} +set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports {GPO[*]}] +set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports {GPO[*]}] +set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCLK] +set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 0.000 [get_ports SDCCLK] +set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCS] +set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCS] +set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCmd] +set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCmd] +set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports UARTSout] +set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports UARTSout] +#set_output_delay -clock [get_clocks VIRTUAL_clk_pll_i] -min -add_delay 0.000 [get_ports ddr3_reset_n] +#set_output_delay -clock [get_clocks VIRTUAL_clk_pll_i] -max -add_delay 80.000 [get_ports ddr3_reset_n] diff --git a/fpga/constraints/constraints-vcu108.xdc b/fpga/constraints/constraints-vcu108.xdc index 8d59509be..3fbb95f68 100644 --- a/fpga/constraints/constraints-vcu108.xdc +++ b/fpga/constraints/constraints-vcu108.xdc @@ -1,23 +1,20 @@ # The main clocks are all autogenerated by the Xilinx IP -# mmcm_clkout1 is the 22Mhz clock from the DDR4 IP used to drive wally and the AHBLite Bus. +# mmcm_clkout1 is the 50Mhz clock from the DDR4 IP used to drive wally and the AHBLite Bus. # mmcm_clkout0 is the clock output of the DDR4 memory interface / 4. # This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP. -# create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O] -create_generated_clock -name CLKDiv64_Gen -source [get_pins xlnx_ddr4_c0/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins axiSDC/clock_posedge_reg/Q] - ##### GPI #### set_property PACKAGE_PIN E34 [get_ports {GPI[0]}] set_property PACKAGE_PIN M22 [get_ports {GPI[1]}] set_property PACKAGE_PIN AW27 [get_ports {GPI[2]}] -set_property PACKAGE_PIN A10 [get_ports {GPI[3]}] -set_property IOSTANDARD LVCMOS12 [get_ports {GPI[3]}] +#set_property PACKAGE_PIN A10 [get_ports {GPI[3]}] +#set_property IOSTANDARD LVCMOS12 [get_ports {GPI[3]}] set_property IOSTANDARD LVCMOS12 [get_ports {GPI[2]}] set_property IOSTANDARD LVCMOS12 [get_ports {GPI[1]}] set_property IOSTANDARD LVCMOS12 [get_ports {GPI[0]}] set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {GPI[*]}] set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports {GPI[*]}] -set_max_delay -from [get_ports {GPI[*]}] 10.000n +set_max_delay -from [get_ports {GPI[*]}] 10.000 ##### GPO #### set_property PACKAGE_PIN AT32 [get_ports {GPO[0]}] @@ -58,7 +55,7 @@ set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_port set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports reset] set_max_delay -from [get_ports reset] 15.000 set_false_path -from [get_ports reset] -set_property PACKAGE_PIN E34 [get_ports {reset}] +set_property PACKAGE_PIN A10 [get_ports {reset}] set_property IOSTANDARD LVCMOS12 [get_ports {reset}] @@ -69,15 +66,6 @@ set_property IOSTANDARD LVCMOS12 [get_ports {cpu_reset}] set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {cpu_reset}] set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {cpu_reset}] - -##### calib ##### -set_property PACKAGE_PIN BA37 [get_ports calib] -set_property IOSTANDARD LVCMOS12 [get_ports calib] -set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports calib] -set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports calib] -set_max_delay -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_ports calib] 50.000 - - ##### ahblite_resetn ##### set_property PACKAGE_PIN AV36 [get_ports {ahblite_resetn}] set_property IOSTANDARD LVCMOS12 [get_ports {ahblite_resetn}] @@ -94,48 +82,31 @@ set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_port ##### SD Card I/O ##### -# set_property PACKAGE_PIN BC14 [get_ports {SDCDat[3]}] -# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[3]}] -# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[2]}] -# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[1]}] -# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[0]}] -# set_property PACKAGE_PIN BF7 [get_ports {SDCDat[2]}] -# set_property PACKAGE_PIN BC13 [get_ports {SDCDat[1]}] -# set_property PACKAGE_PIN AW16 [get_ports {SDCDat[0]}] -# set_property IOSTANDARD LVCMOS18 [get_ports SDCCLK] -# set_property IOSTANDARD LVCMOS18 [get_ports {SDCCmd}] -# set_property PACKAGE_PIN BB16 [get_ports SDCCLK] -# set_property PACKAGE_PIN BA10 [get_ports {SDCCmd}] -# set_property PULLUP true [get_ports {SDCDat[3]}] -# set_property PULLUP true [get_ports {SDCDat[2]}] -# set_property PULLUP true [get_ports {SDCDat[1]}] -# set_property PULLUP true [get_ports {SDCDat[0]}] -# set_property PULLUP true [get_ports {SDCCmd}] +# create the generated SPICLK +#create_generated_clock -name SPISDCClock -source [get_pins ddr4/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncoregen.uncore/spi.spi/SPICLK] -set_property -dict {PACKAGE_PIN BC14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[3]}] -set_property -dict {PACKAGE_PIN BF7 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[2]}] -set_property -dict {PACKAGE_PIN BC13 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[1]}] -set_property -dict {PACKAGE_PIN AW16 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[0]}] +set_output_delay -clock [get_clocks mmcm_clkout1] 0 [get_ports {SDCCS}] +set_input_delay -clock [get_clocks mmcm_clkout1] 0 [get_ports {SDCIn}] +set_output_delay -clock [get_clocks mmcm_clkout1] 0 [get_ports {SDCCmd}] +set_output_delay -clock [get_clocks mmcm_clkout1] 0.000 [get_ports SDCCLK] + + +set_property -dict {PACKAGE_PIN BC14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCS}] +set_property -dict {PACKAGE_PIN AW16 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCIn}] set_property -dict {PACKAGE_PIN BA10 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCmd}] set_property -dict {PACKAGE_PIN AW12 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCD}] set_property -dict {PACKAGE_PIN BB16 IOSTANDARD LVCMOS18} [get_ports SDCCLK] - -set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}] -set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 21.000 [get_ports {SDCDat[*]}] - -set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCCmd}] -set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 14.000 [get_ports {SDCCmd}] - - -set_output_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.000 [get_ports {SDCCmd}] -set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_ports {SDCCmd}] - -set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK] +set_property PACKAGE_PIN AW12 [get_ports SDCCD] +set_property IOSTANDARD LVCMOS18 [get_ports SDCCD] +set_property PULLTYPE PULLUP [get_ports SDCCD] +set_property PACKAGE_PIN BC16 [get_ports SDCWP] +set_property IOSTANDARD LVCMOS18 [get_ports SDCWP] +set_property PULLTYPE PULLUP [get_ports SDCWP] -set_property DCI_CASCADE {64} [get_iobanks 65] +#set_property DCI_CASCADE {64} [get_iobanks 65] set_property INTERNAL_VREF 0.9 [get_iobanks 65] @@ -264,8 +235,8 @@ set_property PACKAGE_PIN D27 [get_ports {c0_ddr4_dm_dbi_n[7]}] set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000 -set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n] -set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports c0_ddr4_reset_n] +#set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n] +#set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports c0_ddr4_reset_n] diff --git a/fpga/constraints/marked_debug.txt b/fpga/constraints/marked_debug.txt index afed3dd23..e0e6ab288 100644 --- a/fpga/constraints/marked_debug.txt +++ b/fpga/constraints/marked_debug.txt @@ -3,8 +3,20 @@ wally/wallypipelinedcore.sv: logic TrapM wally/wallypipelinedcore.sv: logic InstrValidM wally/wallypipelinedcore.sv: logic InstrM lsu/lsu.sv: logic IEUAdrM -lsu/lsu.sv: logic PAdrM -lsu/lsu.sv: logic ReadDataM -lsu/lsu.sv: logic WriteDataM lsu/lsu.sv: logic MemRWM -privileged/csrc.sv: logic HPMCOUNTER_REGW +mmu/hptw.sv: logic SATP_REGW +uncore/spi_apb.sv: logic ShiftIn +uncore/spi_apb.sv: logic ReceiveShiftReg +uncore/spi_apb.sv: logic SCLKenable +uncore/spi_apb.sv: logic SampleEdge +uncore/spi_apb.sv: logic Active +uncore/spi_apb.sv: statetype state +uncore/spi_apb.sv: typedef rsrstatetype +uncore/spi_apb.sv: logic SPICLK +uncore/spi_apb.sv: logic SPIOut +uncore/spi_apb.sv: logic SPICS +uncore/spi_apb.sv: logic SckMode +uncore/spi_apb.sv: logic SckDiv +uncore/spi_apb.sv: logic ShiftEdge +uncore/spi_apb.sv: logic TransmitShiftRegLoad +uncore/spi_apb.sv: logic TransmitShiftReg diff --git a/fpga/constraints/marked_debug_rvvi.txt b/fpga/constraints/marked_debug_rvvi.txt new file mode 100644 index 000000000..afed3dd23 --- /dev/null +++ b/fpga/constraints/marked_debug_rvvi.txt @@ -0,0 +1,10 @@ +wally/wallypipelinedcore.sv: logic PCM +wally/wallypipelinedcore.sv: logic TrapM +wally/wallypipelinedcore.sv: logic InstrValidM +wally/wallypipelinedcore.sv: logic InstrM +lsu/lsu.sv: logic IEUAdrM +lsu/lsu.sv: logic PAdrM +lsu/lsu.sv: logic ReadDataM +lsu/lsu.sv: logic WriteDataM +lsu/lsu.sv: logic MemRWM +privileged/csrc.sv: logic HPMCOUNTER_REGW diff --git a/fpga/constraints/vcu-small-debug.xdc b/fpga/constraints/vcu-small-debug.xdc index 62fea508f..0ce1152f3 100644 --- a/fpga/constraints/vcu-small-debug.xdc +++ b/fpga/constraints/vcu-small-debug.xdc @@ -1,6 +1,6 @@ create_debug_core u_ila_0 ila -set_property C_DATA_DEPTH 2048 [get_debug_cores u_ila_0] +set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_0] set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile index 3f33d55dd..1d0fcc6bc 100644 --- a/fpga/generator/Makefile +++ b/fpga/generator/Makefile @@ -27,19 +27,15 @@ FPGA_VCU: PreProcessFiles IP_VCU # Generate IP Blocks .PHONY: IP_Arty IP_VCU -IP_VCU: $(dst)/xlnx_proc_sys_reset.log \ +IP_VCU: $(dst)/sysrst.log \ MEM_VCU \ - $(dst)/xlnx_axi_clock_converter.log \ - $(dst)/xlnx_ahblite_axi_bridge.log \ - $(dst)/xlnx_axi_crossbar.log \ - $(dst)/xlnx_axi_dwidth_conv_32to64.log \ - $(dst)/xlnx_axi_dwidth_conv_64to32.log \ - $(dst)/xlnx_axi_prtcl_conv.log -IP_Arty: $(dst)/xlnx_proc_sys_reset.log \ + $(dst)/clkconverter.log \ + $(dst)/ahbaxibridge.log +IP_Arty: $(dst)/sysrst.log \ MEM_Arty \ $(dst)/xlnx_mmcm.log \ - $(dst)/xlnx_axi_clock_converter.log \ - $(dst)/xlnx_ahblite_axi_bridge.log + $(dst)/clkconverter.log \ + $(dst)/ahbaxibridge.log #$(dst)/xlnx_axi_crossbar.log \ #$(dst)/xlnx_axi_dwidth_conv_32to64.log \ #$(dst)/xlnx_axi_dwidth_conv_64to32.log \ @@ -48,9 +44,9 @@ IP_Arty: $(dst)/xlnx_proc_sys_reset.log \ # Generate Memory IP Blocks .PHONY: MEM_VCU MEM_Arty MEM_VCU: - $(MAKE) $(dst)/xlnx_ddr4-$(board).log + $(MAKE) $(dst)/ddr4-$(board).log MEM_Arty: - $(MAKE) $(dst)/xlnx_ddr3-$(board).log + $(MAKE) $(dst)/ddr3-$(board).log # Copy files and make necessary modifications .PHONY: PreProcessFiles diff --git a/fpga/generator/xlnx_ahblite_axi_bridge.tcl b/fpga/generator/ahbaxibridge.tcl similarity index 78% rename from fpga/generator/xlnx_ahblite_axi_bridge.tcl rename to fpga/generator/ahbaxibridge.tcl index 946e23174..e41eed6ce 100644 --- a/fpga/generator/xlnx_ahblite_axi_bridge.tcl +++ b/fpga/generator/ahbaxibridge.tcl @@ -2,15 +2,7 @@ set partNumber $::env(XILINX_PART) set boardName $::env(XILINX_BOARD) -# vcu118 board -#set partNumber xcvu9p-flga2104-2L-e -#set boardName xilinx.com:vcu118:part0:2.4 - -# kcu105 board -#set partNumber xcku040-ffva1156-2-e -#set boardName xilinx.com:kcu105:part0:1.7 - -set ipName xlnx_ahblite_axi_bridge +set ipName ahbaxibridge create_project $ipName . -force -part $partNumber if {$boardName!="ArtyA7"} { diff --git a/fpga/generator/xlnx_axi_clock_converter.tcl b/fpga/generator/clkconverter.tcl similarity index 96% rename from fpga/generator/xlnx_axi_clock_converter.tcl rename to fpga/generator/clkconverter.tcl index 87a199cb7..6a9746504 100644 --- a/fpga/generator/xlnx_axi_clock_converter.tcl +++ b/fpga/generator/clkconverter.tcl @@ -4,7 +4,7 @@ set boardName $::env(XILINX_BOARD) #set partNumber xcvu9p-flga2104-2L-e #set boardName xilinx.com:vcu118:part0:2.4 -set ipName xlnx_axi_clock_converter +set ipName clkconverter create_project $ipName . -force -part $partNumber if {$boardName!="ArtyA7"} { diff --git a/fpga/generator/xlnx_ddr3-ArtyA7.tcl b/fpga/generator/ddr3-ArtyA7.tcl similarity index 97% rename from fpga/generator/xlnx_ddr3-ArtyA7.tcl rename to fpga/generator/ddr3-ArtyA7.tcl index 2213e7da9..20aed4e9f 100644 --- a/fpga/generator/xlnx_ddr3-ArtyA7.tcl +++ b/fpga/generator/ddr3-ArtyA7.tcl @@ -2,7 +2,7 @@ set partNumber $::env(XILINX_PART) set boardName $::env(XILINX_BOARD) -set ipName xlnx_ddr3 +set ipName ddr3 create_project $ipName . -force -part $partNumber set_property board_part $boardName [current_project] diff --git a/fpga/generator/xlnx_ddr4-vcu108.tcl b/fpga/generator/ddr4-vcu108.tcl similarity index 93% rename from fpga/generator/xlnx_ddr4-vcu108.tcl rename to fpga/generator/ddr4-vcu108.tcl index 71f8f06a4..63c849729 100644 --- a/fpga/generator/xlnx_ddr4-vcu108.tcl +++ b/fpga/generator/ddr4-vcu108.tcl @@ -4,7 +4,7 @@ set boardName $::env(XILINX_BOARD) #set partNumber xcvu9p-flga2104-2L-e #set boardName xilinx.com:vcu118:part0:2.4 -set ipName xlnx_ddr4 +set ipName ddr4 create_project $ipName . -force -part $partNumber set_property board_part $boardName [current_project] @@ -15,12 +15,12 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \ CONFIG.No_Controller {1} \ CONFIG.Phy_Only {Complete_Memory_Controller} \ CONFIG.C0.DDR4_PhyClockRatio {4:1} \ - CONFIG.C0.DDR4_TimePeriod {1200} \ + CONFIG.C0.DDR4_TimePeriod {833} \ CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-083E} \ CONFIG.C0.DDR4_BurstLength {8} \ CONFIG.C0.DDR4_BurstType {Sequential} \ - CONFIG.C0.DDR4_CasLatency {13} \ - CONFIG.C0.DDR4_CasWriteLatency {10} \ + CONFIG.C0.DDR4_CasLatency {16} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ CONFIG.C0.DDR4_Slot {Single} \ CONFIG.C0.DDR4_MemoryVoltage {1.2V} \ CONFIG.C0.DDR4_DataWidth {64} \ @@ -36,14 +36,11 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \ CONFIG.C0.DDR4_AxiIDWidth {4} \ CONFIG.C0.DDR4_AxiAddressWidth {31} \ CONFIG.C0.DDR4_AxiNarrowBurst {false} \ - CONFIG.C0.DDR4_CLKFBOUT_MULT {5} \ - CONFIG.C0.DDR4_DIVCLK_DIVIDE {1} \ - CONFIG.C0.DDR4_CLKOUT0_DIVIDE {6} \ CONFIG.Reference_Clock {Differential} \ CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \ - CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {22} \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {50} \ CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \ - CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {208} \ + CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \ CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \ CONFIG.ADDN_UI_CLKOUT3_FREQ_HZ {None} \ CONFIG.ADDN_UI_CLKOUT4.INSERT_VIP {0} \ @@ -106,7 +103,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \ CONFIG.C0.DDR4_CustomParts {no_file_loaded} \ CONFIG.C0.DDR4_EN_PARITY {false} \ CONFIG.C0.DDR4_Enable_LVAUX {false} \ - CONFIG.C0.DDR4_InputClockPeriod {3359} \ + CONFIG.C0.DDR4_InputClockPeriod {3332} \ CONFIG.C0.DDR4_LR_SKEW_0 {0} \ CONFIG.C0.DDR4_LR_SKEW_1 {0} \ CONFIG.C0.DDR4_MemoryName {MainMemory} \ @@ -115,6 +112,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \ CONFIG.C0.DDR4_ODT_SKEW_2 {0} \ CONFIG.C0.DDR4_ODT_SKEW_3 {0} \ CONFIG.C0.DDR4_OnDieTermination {RZQ/6} \ + CONFIG.C0.DDR4_OutputDriverImpedenceControl {RZQ/7} \ CONFIG.C0.DDR4_PAR_SKEW {0} \ CONFIG.C0.DDR4_Specify_MandD {false} \ CONFIG.C0.DDR4_TREFI {0} \ diff --git a/fpga/generator/xlnx_ddr4-vcu118.tcl b/fpga/generator/ddr4-vcu118.tcl similarity index 99% rename from fpga/generator/xlnx_ddr4-vcu118.tcl rename to fpga/generator/ddr4-vcu118.tcl index 8041726ff..5a98c07de 100644 --- a/fpga/generator/xlnx_ddr4-vcu118.tcl +++ b/fpga/generator/ddr4-vcu118.tcl @@ -4,7 +4,7 @@ set boardName $::env(XILINX_BOARD) #set partNumber xcvu9p-flga2104-2L-e #set boardName xilinx.com:vcu118:part0:2.4 -set ipName xlnx_ddr4 +set ipName ddr4 create_project $ipName . -force -part $partNumber set_property board_part $boardName [current_project] diff --git a/fpga/generator/xlnx_mmcm.tcl b/fpga/generator/mmcm.tcl similarity index 93% rename from fpga/generator/xlnx_mmcm.tcl rename to fpga/generator/mmcm.tcl index 146a9cf41..de4a1a1d0 100644 --- a/fpga/generator/xlnx_mmcm.tcl +++ b/fpga/generator/mmcm.tcl @@ -1,7 +1,7 @@ set partNumber $::env(XILINX_PART) set boardName $::env(XILINX_BOARD) -set ipName xlnx_mmcm +set ipName mmcm create_project $ipName . -force -part $partNumber set_property board_part $boardName [current_project] @@ -15,7 +15,7 @@ set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \ CONFIG.CLKOUT4_USED {true} \ CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \ CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \ - CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {25} \ CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {25} \ CONFIG.CLKIN1_JITTER_PS {10.0} \ ] [get_ips $ipName] diff --git a/fpga/generator/xlnx_proc_sys_reset.tcl b/fpga/generator/sysrst.tcl similarity index 96% rename from fpga/generator/xlnx_proc_sys_reset.tcl rename to fpga/generator/sysrst.tcl index 06ca4fb1f..8225c02d5 100644 --- a/fpga/generator/xlnx_proc_sys_reset.tcl +++ b/fpga/generator/sysrst.tcl @@ -4,7 +4,7 @@ set boardName $::env(XILINX_BOARD) #set partNumber xcvu9p-flga2104-2L-e #set boardName xilinx.com:vcu118:part0:2.4 -set ipName xlnx_proc_sys_reset +set ipName sysrst create_project $ipName . -force -part $partNumber if {$boardName!="ArtyA7"} { diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index a5e60a3d5..5207680df 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -5,6 +5,16 @@ set boardName $::env(XILINX_BOARD) set boardSubName [lindex [split ${boardName} :] 1] set board $::env(board) +#set partNumber xc7a100tcsg324-1 +#set boardName digilentinc.com:arty-a7-100:part0:1.1 +#set boardSubName arty-a7-100 +#set board ArtyA7 + +#set partNumber xcvu095-ffva2104-2-e +#set boardName xilinx.com:vcu108:part0:1.7 +#set boardSubName vcu108 +#set board FPU_VCU + set ipName WallyFPGA create_project $ipName . -force -part $partNumber @@ -13,46 +23,32 @@ if {$boardName!="ArtyA7"} { } # read package first -read_verilog -sv ../src/CopiedFiles_do_not_add_to_repo/cvw.sv +add_files ../src/CopiedFiles_do_not_add_to_repo/cvw.sv #read_verilog -sv ../src/wallypipelinedsocwrapper.sv # then read top level if {$board=="ArtyA7"} { - read_verilog {../src/fpgaTopArtyA7.sv} + add_files {../src/fpgaTopArtyA7.sv} } else { - read_verilog {../src/fpgaTop.sv} + add_files {../src/fpgaTop.sv} } # read in ip -read_ip IP/xlnx_proc_sys_reset.srcs/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xci -read_ip IP/xlnx_ahblite_axi_bridge.srcs/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge.xci -read_ip IP/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter.xci -# Added crossbar - Jacob Pease <2023-01-12 Thu> -#read_ip IP/xlnx_axi_crossbar.srcs/sources_1/ip/xlnx_axi_crossbar/xlnx_axi_crossbar.xci -#read_ip IP/xlnx_axi_dwidth_conv_32to64.srcs/sources_1/ip/xlnx_axi_dwidth_conv_32to64/xlnx_axi_dwidth_conv_32to64.xci -#read_ip IP/xlnx_axi_dwidth_conv_64to32.srcs/sources_1/ip/xlnx_axi_dwidth_conv_64to32/xlnx_axi_dwidth_conv_64to32.xci -#read_ip IP/xlnx_axi_prtcl_conv.srcs/sources_1/ip/xlnx_axi_prtcl_conv/xlnx_axi_prtcl_conv.xci +import_ip IP/sysrst.srcs/sources_1/ip/sysrst/sysrst.xci +import_ip IP/ahbaxibridge.srcs/sources_1/ip/ahbaxibridge/ahbaxibridge.xci +import_ip IP/clkconverter.srcs/sources_1/ip/clkconverter/clkconverter.xci if {$board=="ArtyA7"} { - read_ip IP/xlnx_ddr3.srcs/sources_1/ip/xlnx_ddr3/xlnx_ddr3.xci - read_ip IP/xlnx_mmcm.srcs/sources_1/ip/xlnx_mmcm/xlnx_mmcm.xci + import_ip IP/ddr3.srcs/sources_1/ip/ddr3/ddr3.xci + import_ip IP/mmcm.srcs/sources_1/ip/mmcm/mmcm.xci } else { - read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci + import_ip IP/ddr4.srcs/sources_1/ip/ddr4/ddr4.xci } # read in all other rtl -read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv] -# *** Once the sdc is updated to use ahb changes these to system verilog. -read_verilog [glob -type f ../../addins/ahbsdc/sdc/*.v] +add_files [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv] set_property include_dirs {../src/CopiedFiles_do_not_add_to_repo/config ../../config/shared ../../addins/ahbsdc/sdc} [current_fileset] -if {$board=="ArtyA7"} { - add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc - set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$board.xdc] -} else { - add_files -fileset constrs_1 -norecurse ../constraints/constraints-$boardSubName.xdc - set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$boardSubName.xdc] -} # define top level set_property top fpgaTop [current_fileset] @@ -62,12 +58,21 @@ update_compile_order -fileset sources_1 exec mkdir -p reports/ exec rm -rf reports/* + report_compile_order -constraints > reports/compile_order.rpt # this is elaboration not synthesis. -synth_design -rtl -name rtl_1 -flatten_hierarchy none +#synth_design -rtl -name rtl_1 -flatten_hierarchy none + +# apply timing constraint after elaboration +if {$board=="ArtyA7"} { + add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc + set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$board.xdc] +} else { + add_files -fileset constrs_1 -norecurse ../constraints/constraints-$boardSubName.xdc + set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$boardSubName.xdc] +} -report_clocks -file reports/clocks.rpt # Temp set_param messaging.defaultLimit 100000 @@ -79,6 +84,8 @@ launch_runs synth_1 -jobs 16 wait_on_run synth_1 open_run synth_1 +report_clocks -file reports/clocks.rpt + check_timing -verbose -file reports/check_timing.rpt report_timing -max_paths 10 -nworst 10 -delay_type max -sort_by slack -file reports/timing_WORST_10.rpt report_timing -nworst 1 -delay_type max -sort_by group -file reports/timing.rpt @@ -89,10 +96,12 @@ report_clock_interaction -file re write_verilog -force -mode funcsim sim/syn-funcsim.v if {$board=="ArtyA7"} { - source ../constraints/small-debug.xdc + #source ../constraints/small-debug.xdc #source ../constraints/small-debug-rvvi.xdc } else { - source ../constraints/vcu-small-debug.xdc + #source ../constraints/vcu-small-debug.xdc + #source ../constraints/small-debug.xdc + source ../constraints/small-debug-spi.xdc } diff --git a/fpga/generator/xlnx_axi_crossbar.tcl b/fpga/generator/xlnx_axi_crossbar.tcl deleted file mode 100644 index 1d9eb4e78..000000000 --- a/fpga/generator/xlnx_axi_crossbar.tcl +++ /dev/null @@ -1,32 +0,0 @@ -set partNumber $::env(XILINX_PART) -set boardName $::env(XILINX_BOARD) - -# vcu118 board -#set partNumber xcvu9p-flga2104-2L-e -#set boardName xilinx.com:vcu118:part0:2.4 - -# kcu105 board -#set partNumber xcku040-ffva1156-2-e -#set boardName xilinx.com:kcu105:part0:1.7 - -set ipName xlnx_axi_crossbar - -create_project $ipName . -force -part $partNumber -set_property board_part $boardName [current_project] - -create_ip -name axi_crossbar -vendor xilinx.com -library ip -version 2.1 -module_name $ipName - -set_property -dict [list CONFIG.NUM_SI {2} \ - CONFIG.DATA_WIDTH {64} \ - CONFIG.ID_WIDTH {4} \ - CONFIG.M01_S01_READ_CONNECTIVITY {0} \ - CONFIG.M01_S01_WRITE_CONNECTIVITY {0} \ - CONFIG.M00_A00_BASE_ADDR {0x0000000080000000} \ - CONFIG.M01_A00_BASE_ADDR {0x0000000000013000} \ - CONFIG.M00_A00_ADDR_WIDTH {31}] [get_ips $ipName] - -generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -launch_run -jobs 8 ${ipName}_synth_1 -wait_on_run ${ipName}_synth_1 diff --git a/fpga/generator/xlnx_axi_dwidth_conv_32to64.tcl b/fpga/generator/xlnx_axi_dwidth_conv_32to64.tcl deleted file mode 100644 index 97edd97d9..000000000 --- a/fpga/generator/xlnx_axi_dwidth_conv_32to64.tcl +++ /dev/null @@ -1,25 +0,0 @@ -set partNumber $::env(XILINX_PART) -set boardName $::env(XILINX_BOARD) - -# vcu118 board -#set partNumber xcvu9p-flga2104-2L-e -#set boardName xilinx.com:vcu118:part0:2.4 - -# kcu105 board -#set partNumber xcku040-ffva1156-2-e -#set boardName xilinx.com:kcu105:part0:1.7 - -set ipName xlnx_axi_dwidth_conv_32to64 - -create_project $ipName . -force -part $partNumber -set_property board_part $boardName [current_project] - -create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName - -set_property -dict [list CONFIG.Component_Name {axi_dwidth_conv_32to64}] [get_ips $ipName] - -generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -launch_run -jobs 8 ${ipName}_synth_1 -wait_on_run ${ipName}_synth_1 diff --git a/fpga/generator/xlnx_axi_dwidth_conv_64to32.tcl b/fpga/generator/xlnx_axi_dwidth_conv_64to32.tcl deleted file mode 100644 index 3883a8a9d..000000000 --- a/fpga/generator/xlnx_axi_dwidth_conv_64to32.tcl +++ /dev/null @@ -1,27 +0,0 @@ -set partNumber $::env(XILINX_PART) -set boardName $::env(XILINX_BOARD) - -# vcu118 board -#set partNumber xcvu9p-flga2104-2L-e -#set boardName xilinx.com:vcu118:part0:2.4 - -# kcu105 board -#set partNumber xcku040-ffva1156-2-e -#set boardName xilinx.com:kcu105:part0:1.7 - -set ipName xlnx_axi_dwidth_conv_64to32 - -create_project $ipName . -force -part $partNumber -set_property board_part $boardName [current_project] - -create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName - -set_property -dict [list CONFIG.Component_Name {axi_dwidth_conv_64to32} \ - CONFIG.SI_DATA_WIDTH {64} \ - CONFIG.MI_DATA_WIDTH {32}] [get_ips $ipName] - -generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -launch_run -jobs 8 ${ipName}_synth_1 -wait_on_run ${ipName}_synth_1 diff --git a/fpga/generator/xlnx_axi_dwidth_converter.tcl b/fpga/generator/xlnx_axi_dwidth_converter.tcl deleted file mode 100644 index ba979bf01..000000000 --- a/fpga/generator/xlnx_axi_dwidth_converter.tcl +++ /dev/null @@ -1,25 +0,0 @@ -set partNumber $::env(XILINX_PART) -set boardName $::env(XILINX_BOARD) - -# vcu118 board -#set partNumber xcvu9p-flga2104-2L-e -#set boardName xilinx.com:vcu118:part0:2.4 - -# kcu105 board -#set partNumber xcku040-ffva1156-2-e -#set boardName xilinx.com:kcu105:part0:1.7 - -set ipName xlnx_axi_dwidth_converter - -create_project $ipName . -force -part $partNumber -set_property board_part $boardName [current_project] - -create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName - -set_property -dict [list CONFIG.Component_Name {axi_dwidth_converter}] [get_ips $ipName] - -generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -launch_run -jobs 8 ${ipName}_synth_1 -wait_on_run ${ipName}_synth_1 diff --git a/fpga/generator/xlnx_axi_prtcl_conv.tcl b/fpga/generator/xlnx_axi_prtcl_conv.tcl deleted file mode 100644 index 76b6fc6cd..000000000 --- a/fpga/generator/xlnx_axi_prtcl_conv.tcl +++ /dev/null @@ -1,23 +0,0 @@ -set partNumber $::env(XILINX_PART) -set boardName $::env(XILINX_BOARD) - -# vcu118 board -#set partNumber xcvu9p-flga2104-2L-e -#set boardName xilinx.com:vcu118:part0:2.4 - -# kcu105 board -#set partNumber xcku040-ffva1156-2-e -#set boardName xilinx.com:kcu105:part0:1.7 - -set ipName xlnx_axi_prtcl_conv - -create_project $ipName . -force -part $partNumber -set_property board_part $boardName [current_project] - -create_ip -name axi_protocol_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName - -generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -launch_run -jobs 8 ${ipName}_synth_1 -wait_on_run ${ipName}_synth_1 diff --git a/fpga/generator/xlnx_ddr4.tcl b/fpga/generator/xlnx_ddr4.tcl index c3aac1f71..2b9d24e70 100644 --- a/fpga/generator/xlnx_ddr4.tcl +++ b/fpga/generator/xlnx_ddr4.tcl @@ -5,7 +5,7 @@ set partNumber xcvu095-ffva2104-2-e set boardName xilinx.com:vcu108:part0:1.2 -set ipName xlnx_ddr4 +set ipName ddr4 create_project $ipName . -force -part $partNumber set_property board_part $boardName [current_project] diff --git a/fpga/src/fpgaTop.sv b/fpga/src/fpgaTop.sv index 20ffd4b08..9ae282966 100644 --- a/fpga/src/fpgaTop.sv +++ b/fpga/src/fpgaTop.sv @@ -34,18 +34,20 @@ module fpgaTop input reset, input south_rst, - input [3:0] GPI, + input [2:0] GPI, output [4:0] GPO, input UARTSin, output UARTSout, - inout [3:0] SDCDat, - output SDCCLK, - inout SDCCmd, - input SDCCD, + // SDC Signals connecting to an SPI peripheral + input SDCIn, + output SDCCLK, + output SDCCmd, + output SDCCS, + input SDCCD, + input SDCWP, - output calib, output cpu_reset, output ahblite_resetn, @@ -65,414 +67,133 @@ module fpgaTop output [0 : 0] c0_ddr4_ck_t ); - wire CPUCLK; - wire c0_ddr4_ui_clk_sync_rst; - wire bus_struct_reset; - wire peripheral_reset; - wire interconnect_aresetn; - wire peripheral_aresetn; - wire mb_reset; - - wire HCLKOpen; - wire HRESETnOpen; - wire [64-1:0] HRDATAEXT; - wire HREADYEXT; - wire HRESPEXT; - (* mark_debug = "true" *) wire HSELEXT; - (* mark_debug = "true" *) wire HSELEXTSDC; // TEMP BOOT SIGNAL - JACOB - wire [55:0] HADDR; - wire [64-1:0] HWDATA; - wire [64/8-1:0] HWSTRB; - wire HWRITE; - wire [2:0] HSIZE; - wire [2:0] HBURST; - wire [1:0] HTRANS; - wire HREADY; - wire [3:0] HPROT; - wire HMASTLOCK; - + logic CPUCLK; + logic c0_ddr4_ui_clk_sync_rst; + logic bus_struct_reset; + logic peripheral_reset; + logic interconnect_aresetn; + logic peripheral_aresetn; + logic mb_reset; + logic HCLKOpen; + logic HRESETnOpen; + logic [64-1:0] HRDATAEXT; + logic HREADYEXT; + logic HRESPEXT; + logic HSELEXT; + logic [55:0] HADDR; + logic [64-1:0] HWDATA; + logic [64/8-1:0] HWSTRB; + logic HWRITE; + logic [2:0] HSIZE; + logic [2:0] HBURST; + logic [1:0] HTRANS; + logic HREADY; + logic [3:0] HPROT; + logic HMASTLOCK; - wire [31:0] GPIOIN, GPIOOUT, GPIOEN; + logic RVVIStall; - // Old SDC connections - // wire SDCCmdIn; - // wire SDCCmdOE; - // wire SDCCmdOut; + logic [31:0] GPIOIN, GPIOOUT, GPIOEN; - (* mark_debug = "true" *)wire [3:0] m_axi_awid; - (* mark_debug = "true" *)wire [7:0] m_axi_awlen; - (* mark_debug = "true" *)wire [2:0] m_axi_awsize; - (* mark_debug = "true" *)wire [1:0] m_axi_awburst; - (* mark_debug = "true" *)wire [3:0] m_axi_awcache; - (* mark_debug = "true" *)wire [31:0] m_axi_awaddr; - (* mark_debug = "true" *)wire [2:0] m_axi_awprot; - (* mark_debug = "true" *)wire m_axi_awvalid; - (* mark_debug = "true" *)wire m_axi_awready; - (* mark_debug = "true" *)wire m_axi_awlock; - (* mark_debug = "true" *)wire [63:0] m_axi_wdata; - (* mark_debug = "true" *)wire [7:0] m_axi_wstrb; - (* mark_debug = "true" *)wire m_axi_wlast; - (* mark_debug = "true" *)wire m_axi_wvalid; - (* mark_debug = "true" *)wire m_axi_wready; - (* mark_debug = "true" *)wire [3:0] m_axi_bid; - (* mark_debug = "true" *)wire [1:0] m_axi_bresp; - (* mark_debug = "true" *)wire m_axi_bvalid; - (* mark_debug = "true" *)wire m_axi_bready; - (* mark_debug = "true" *)wire [3:0] m_axi_arid; - (* mark_debug = "true" *)wire [7:0] m_axi_arlen; - (* mark_debug = "true" *)wire [2:0] m_axi_arsize; - (* mark_debug = "true" *)wire [1:0] m_axi_arburst; - (* mark_debug = "true" *)wire [2:0] m_axi_arprot; - (* mark_debug = "true" *)wire [3:0] m_axi_arcache; - (* mark_debug = "true" *)wire m_axi_arvalid; - (* mark_debug = "true" *)wire [31:0] m_axi_araddr; - (* mark_debug = "true" *)wire m_axi_arlock; - (* mark_debug = "true" *)wire m_axi_arready; - (* mark_debug = "true" *)wire [3:0] m_axi_rid; - (* mark_debug = "true" *)wire [63:0] m_axi_rdata; - (* mark_debug = "true" *)wire [1:0] m_axi_rresp; - (* mark_debug = "true" *)wire m_axi_rvalid; - (* mark_debug = "true" *)wire m_axi_rlast; - (* mark_debug = "true" *)wire m_axi_rready; + logic [3:0] m_axi_awid; + logic [7:0] m_axi_awlen; + logic [2:0] m_axi_awsize; + logic [1:0] m_axi_awburst; + logic [3:0] m_axi_awcache; + logic [31:0] m_axi_awaddr; + logic [2:0] m_axi_awprot; + logic m_axi_awvalid; + logic m_axi_awready; + logic m_axi_awlock; + logic [63:0] m_axi_wdata; + logic [7:0] m_axi_wstrb; + logic m_axi_wlast; + logic m_axi_wvalid; + logic m_axi_wready; + logic [3:0] m_axi_bid; + logic [1:0] m_axi_bresp; + logic m_axi_bvalid; + logic m_axi_bready; + logic [3:0] m_axi_arid; + logic [7:0] m_axi_arlen; + logic [2:0] m_axi_arsize; + logic [1:0] m_axi_arburst; + logic [2:0] m_axi_arprot; + logic [3:0] m_axi_arcache; + logic m_axi_arvalid; + logic [31:0] m_axi_araddr; + logic m_axi_arlock; + logic m_axi_arready; + logic [3:0] m_axi_rid; + logic [63:0] m_axi_rdata; + logic [1:0] m_axi_rresp; + logic m_axi_rvalid; + logic m_axi_rlast; + logic m_axi_rready; // Extra Bus signals - wire [3:0] BUS_axi_arregion; - wire [3:0] BUS_axi_arqos; - wire [3:0] BUS_axi_awregion; - wire [3:0] BUS_axi_awqos; + logic [3:0] BUS_axi_arregion; + logic [3:0] BUS_axi_arqos; + logic [3:0] BUS_axi_awregion; + logic [3:0] BUS_axi_awqos; // Bus signals - wire [3:0] BUS_axi_awid; - wire [7:0] BUS_axi_awlen; - wire [2:0] BUS_axi_awsize; - wire [1:0] BUS_axi_awburst; - wire [3:0] BUS_axi_awcache; - wire [30:0] BUS_axi_awaddr; - wire [2:0] BUS_axi_awprot; - wire BUS_axi_awvalid; - wire BUS_axi_awready; - wire BUS_axi_awlock; - wire [63:0] BUS_axi_wdata; - wire [7:0] BUS_axi_wstrb; - wire BUS_axi_wlast; - wire BUS_axi_wvalid; - wire BUS_axi_wready; - wire [3:0] BUS_axi_bid; - wire [1:0] BUS_axi_bresp; - wire BUS_axi_bvalid; - wire BUS_axi_bready; - wire [3:0] BUS_axi_arid; - wire [7:0] BUS_axi_arlen; - wire [2:0] BUS_axi_arsize; - wire [1:0] BUS_axi_arburst; - wire [2:0] BUS_axi_arprot; - wire [3:0] BUS_axi_arcache; - wire BUS_axi_arvalid; - wire [30:0] BUS_axi_araddr; - wire BUS_axi_arlock; - wire BUS_axi_arready; - wire [3:0] BUS_axi_rid; - wire [63:0] BUS_axi_rdata; - wire [1:0] BUS_axi_rresp; - wire BUS_axi_rvalid; - wire BUS_axi_rlast; - wire BUS_axi_rready; + logic [3:0] BUS_axi_awid; + logic [7:0] BUS_axi_awlen; + logic [2:0] BUS_axi_awsize; + logic [1:0] BUS_axi_awburst; + logic [3:0] BUS_axi_awcache; + logic [30:0] BUS_axi_awaddr; + logic [2:0] BUS_axi_awprot; + logic BUS_axi_awvalid; + logic BUS_axi_awready; + logic BUS_axi_awlock; + logic [63:0] BUS_axi_wdata; + logic [7:0] BUS_axi_wstrb; + logic BUS_axi_wlast; + logic BUS_axi_wvalid; + logic BUS_axi_wready; + logic [3:0] BUS_axi_bid; + logic [1:0] BUS_axi_bresp; + logic BUS_axi_bvalid; + logic BUS_axi_bready; + logic [3:0] BUS_axi_arid; + logic [7:0] BUS_axi_arlen; + logic [2:0] BUS_axi_arsize; + logic [1:0] BUS_axi_arburst; + logic [2:0] BUS_axi_arprot; + logic [3:0] BUS_axi_arcache; + logic BUS_axi_arvalid; + logic [30:0] BUS_axi_araddr; + logic BUS_axi_arlock; + logic BUS_axi_arready; + logic [3:0] BUS_axi_rid; + logic [63:0] BUS_axi_rdata; + logic [1:0] BUS_axi_rresp; + logic BUS_axi_rvalid; + logic BUS_axi_rlast; + logic BUS_axi_rready; - wire BUSCLK; - + logic BUSCLK; - wire c0_init_calib_complete; - wire dbg_clk; - wire [511 : 0] dbg_bus; + logic c0_init_calib_complete; + logic dbg_clk; + logic [511 : 0] dbg_bus; - wire CLK208; + logic CLK208; - - // Crossbar to Bus ------------------------------------------------ - - (* mark_debug = "true" *)wire s00_axi_aclk; - (* mark_debug = "true" *)wire s00_axi_aresetn; - (* mark_debug = "true" *)wire [3:0] s00_axi_awid; - (* mark_debug = "true" *)wire [31:0]s00_axi_awaddr; - (* mark_debug = "true" *)wire [7:0]s00_axi_awlen; - (* mark_debug = "true" *)wire [2:0]s00_axi_awsize; - (* mark_debug = "true" *)wire [1:0]s00_axi_awburst; - (* mark_debug = "true" *)wire [0:0]s00_axi_awlock; - (* mark_debug = "true" *)wire [3:0]s00_axi_awcache; - (* mark_debug = "true" *)wire [2:0]s00_axi_awprot; - (* mark_debug = "true" *)wire [3:0]s00_axi_awregion; - (* mark_debug = "true" *)wire [3:0]s00_axi_awqos; - (* mark_debug = "true" *) wire s00_axi_awvalid; - (* mark_debug = "true" *) wire s00_axi_awready; - (* mark_debug = "true" *)wire [63:0]s00_axi_wdata; - (* mark_debug = "true" *)wire [7:0]s00_axi_wstrb; - (* mark_debug = "true" *)wire s00_axi_wlast; - (* mark_debug = "true" *)wire s00_axi_wvalid; - (* mark_debug = "true" *)wire s00_axi_wready; - (* mark_debug = "true" *)wire [1:0]s00_axi_bresp; - (* mark_debug = "true" *)wire s00_axi_bvalid; - (* mark_debug = "true" *)wire s00_axi_bready; - (* mark_debug = "true" *)wire [31:0]s00_axi_araddr; - (* mark_debug = "true" *)wire [7:0]s00_axi_arlen; - (* mark_debug = "true" *)wire [2:0]s00_axi_arsize; - (* mark_debug = "true" *)wire [1:0]s00_axi_arburst; - (* mark_debug = "true" *)wire [0:0]s00_axi_arlock; - (* mark_debug = "true" *)wire [3:0]s00_axi_arcache; - (* mark_debug = "true" *)wire [2:0]s00_axi_arprot; - (* mark_debug = "true" *)wire [3:0]s00_axi_arregion; - (* mark_debug = "true" *)wire [3:0]s00_axi_arqos; - (* mark_debug = "true" *)wire s00_axi_arvalid; - (* mark_debug = "true" *)wire s00_axi_arready; - (* mark_debug = "true" *)wire [63:0]s00_axi_rdata; - (* mark_debug = "true" *)wire [1:0]s00_axi_rresp; - (* mark_debug = "true" *)wire s00_axi_rlast; - (* mark_debug = "true" *)wire s00_axi_rvalid; - (* mark_debug = "true" *)wire s00_axi_rready; - - (* mark_debug = "true" *)wire [3:0] s00_axi_bid; - (* mark_debug = "true" *)wire [3:0] s00_axi_rid; - - // 64to32 dwidth converter input interface------------------------- - wire s01_axi_aclk; - wire s01_axi_aresetn; - wire [3:0]s01_axi_awid; - wire [31:0]s01_axi_awaddr; - wire [7:0]s01_axi_awlen; - wire [2:0]s01_axi_awsize; - wire [1:0]s01_axi_awburst; - wire [0:0]s01_axi_awlock; - wire [3:0]s01_axi_awcache; - wire [2:0]s01_axi_awprot; - wire [3:0]s01_axi_awregion; - wire [3:0]s01_axi_awqos; // qos signals need to be 0 for SDC - (* mark_debug = "true" *) wire s01_axi_awvalid; - (* mark_debug = "true" *) wire s01_axi_awready; - wire [63:0]s01_axi_wdata; - wire [7:0]s01_axi_wstrb; - wire s01_axi_wlast; - wire s01_axi_wvalid; - wire s01_axi_wready; - wire [1:0]s01_axi_bresp; - wire s01_axi_bvalid; - wire s01_axi_bready; - wire [31:0]s01_axi_araddr; - wire [7:0]s01_axi_arlen; - wire [2:0]s01_axi_arsize; - wire [1:0]s01_axi_arburst; - wire [0:0]s01_axi_arlock; - wire [3:0]s01_axi_arcache; - wire [2:0]s01_axi_arprot; - wire [3:0]s01_axi_arregion; - wire [3:0]s01_axi_arqos; // - wire s01_axi_arvalid; - wire s01_axi_arready; - wire [63:0]s01_axi_rdata; - wire [1:0]s01_axi_rresp; - wire s01_axi_rlast; - wire s01_axi_rvalid; - wire s01_axi_rready; - - // Output Interface - wire [31:0]axi4in_axi_awaddr; - wire [7:0]axi4in_axi_awlen; - wire [2:0]axi4in_axi_awsize; - wire [1:0]axi4in_axi_awburst; - wire [0:0]axi4in_axi_awlock; - wire [3:0]axi4in_axi_awcache; - wire [2:0]axi4in_axi_awprot; - wire [3:0]axi4in_axi_awregion; - wire [3:0]axi4in_axi_awqos; - (* mark_debug = "true" *) wire axi4in_axi_awvalid; - (* mark_debug = "true" *) wire axi4in_axi_awready; - wire [31:0]axi4in_axi_wdata; - wire [3:0]axi4in_axi_wstrb; - wire axi4in_axi_wlast; - wire axi4in_axi_wvalid; - wire axi4in_axi_wready; - wire [1:0]axi4in_axi_bresp; - wire axi4in_axi_bvalid; - wire axi4in_axi_bready; - wire [31:0]axi4in_axi_araddr; - wire [7:0]axi4in_axi_arlen; - wire [2:0]axi4in_axi_arsize; - wire [1:0]axi4in_axi_arburst; - wire [0:0]axi4in_axi_arlock; - wire [3:0]axi4in_axi_arcache; - wire [2:0]axi4in_axi_arprot; - wire [3:0]axi4in_axi_arregion; - wire [3:0]axi4in_axi_arqos; - wire axi4in_axi_arvalid; - wire axi4in_axi_arready; - wire [31:0]axi4in_axi_rdata; - wire [1:0]axi4in_axi_rresp; - wire axi4in_axi_rlast; - wire axi4in_axi_rvalid; - wire axi4in_axi_rready; - - // AXI4 to AXI4-Lite Protocol converter output - (* mark_debug = "true" *) wire [31:0]SDCin_axi_awaddr; - (* mark_debug = "true" *) wire [2:0]SDCin_axi_awprot; - (* mark_debug = "true" *) wire SDCin_axi_awvalid; - (* mark_debug = "true" *) wire SDCin_axi_awready; - (* mark_debug = "true" *) wire [31:0]SDCin_axi_wdata; - (* mark_debug = "true" *) wire [3:0]SDCin_axi_wstrb; - (* mark_debug = "true" *) wire SDCin_axi_wvalid; - (* mark_debug = "true" *) wire SDCin_axi_wready; - (* mark_debug = "true" *) wire [1:0]SDCin_axi_bresp; - (* mark_debug = "true" *) wire SDCin_axi_bvalid; - (* mark_debug = "true" *) wire SDCin_axi_bready; - (* mark_debug = "true" *) wire [31:0]SDCin_axi_araddr; - (* mark_debug = "true" *) wire [2:0]SDCin_axi_arprot; - (* mark_debug = "true" *) wire SDCin_axi_arvalid; - (* mark_debug = "true" *) wire SDCin_axi_arready; - (* mark_debug = "true" *) wire [31:0]SDCin_axi_rdata; - (* mark_debug = "true" *) wire [1:0]SDCin_axi_rresp; - (* mark_debug = "true" *) wire SDCin_axi_rvalid; - (* mark_debug = "true" *) wire SDCin_axi_rready; - // ---------------------------------------------------------------- - - // 32to64 dwidth converter input interface ----------------------- - (* mark_debug = "true" *) wire [31:0]SDCout_axi_awaddr; - (* mark_debug = "true" *) wire [7:0]SDCout_axi_awlen; - wire [2:0]SDCout_axi_awsize; - wire [1:0]SDCout_axi_awburst; - wire [0:0]SDCout_axi_awlock; - wire [3:0]SDCout_axi_awcache; - wire [2:0]SDCout_axi_awprot; - wire [3:0]SDCout_axi_awregion; - wire [3:0]SDCout_axi_awqos; - (* mark_debug = "true" *) wire SDCout_axi_awvalid; - (* mark_debug = "true" *) wire SDCout_axi_awready; - (* mark_debug = "true" *) wire [31:0]SDCout_axi_wdata; - wire [3:0]SDCout_axi_wstrb; - (* mark_debug = "true" *) wire SDCout_axi_wlast; - (* mark_debug = "true" *) wire SDCout_axi_wvalid; - (* mark_debug = "true" *)wire SDCout_axi_wready; - (* mark_debug = "true" *) wire [1:0]SDCout_axi_bresp; - (* mark_debug = "true" *) wire SDCout_axi_bvalid; - (* mark_debug = "true" *) wire SDCout_axi_bready; - wire [31:0]SDCout_axi_araddr; - wire [7:0]SDCout_axi_arlen; - wire [2:0]SDCout_axi_arsize; - wire [1:0]SDCout_axi_arburst; - wire [0:0]SDCout_axi_arlock; - wire [3:0]SDCout_axi_arcache; - wire [2:0]SDCout_axi_arprot; - wire [3:0]SDCout_axi_arregion; - wire [3:0]SDCout_axi_arqos; - wire SDCout_axi_arvalid; - wire SDCout_axi_arready; - wire [31:0]SDCout_axi_rdata; - wire [1:0]SDCout_axi_rresp; - wire SDCout_axi_rlast; - wire SDCout_axi_rvalid; - wire SDCout_axi_rready; - - // Output Interface - (* mark_debug = "true" *) wire [3:0]m01_axi_awid; - (* mark_debug = "true" *) wire [31:0]m01_axi_awaddr; - (* mark_debug = "true" *) wire [7:0]m01_axi_awlen; - (* mark_debug = "true" *) wire [2:0]m01_axi_awsize; - (* mark_debug = "true" *) wire [1:0]m01_axi_awburst; - (* mark_debug = "true" *) wire [0:0]m01_axi_awlock; - (* mark_debug = "true" *) wire [3:0]m01_axi_awcache; - (* mark_debug = "true" *) wire [2:0]m01_axi_awprot; - (* mark_debug = "true" *) wire [3:0]m01_axi_awregion; - (* mark_debug = "true" *) wire [3:0]m01_axi_awqos; - (* mark_debug = "true" *) wire m01_axi_awvalid; - (* mark_debug = "true" *) wire m01_axi_awready; - (* mark_debug = "true" *) wire [63:0]m01_axi_wdata; - (* mark_debug = "true" *) wire [7:0]m01_axi_wstrb; - (* mark_debug = "true" *) wire m01_axi_wlast; - (* mark_debug = "true" *) wire m01_axi_wvalid; - (* mark_debug = "true" *) wire m01_axi_wready; - (* mark_debug = "true" *) wire [3:0] m01_axi_bid; - (* mark_debug = "true" *) wire [1:0]m01_axi_bresp; - (* mark_debug = "true" *) wire m01_axi_bvalid; - (* mark_debug = "true" *) wire m01_axi_bready; - (* mark_debug = "true" *) wire [3:0] m01_axi_arid; - (* mark_debug = "true" *) wire [31:0]m01_axi_araddr; - (* mark_debug = "true" *) wire [7:0]m01_axi_arlen; - (* mark_debug = "true" *) wire [2:0]m01_axi_arsize; - (* mark_debug = "true" *) wire [1:0]m01_axi_arburst; - (* mark_debug = "true" *) wire [0:0]m01_axi_arlock; - (* mark_debug = "true" *) wire [3:0]m01_axi_arcache; - (* mark_debug = "true" *) wire [2:0]m01_axi_arprot; - (* mark_debug = "true" *) wire [3:0]m01_axi_arregion; - (* mark_debug = "true" *) wire [3:0]m01_axi_arqos; - (* mark_debug = "true" *) wire m01_axi_arvalid; - (* mark_debug = "true" *) wire m01_axi_arready; - (* mark_debug = "true" *) wire [3:0] m01_axi_rid; - (* mark_debug = "true" *) wire [63:0]m01_axi_rdata; - (* mark_debug = "true" *) wire [1:0]m01_axi_rresp; - (* mark_debug = "true" *) wire m01_axi_rlast; - (* mark_debug = "true" *) wire m01_axi_rvalid; - (* mark_debug = "true" *) wire m01_axi_rready; - - // Old SDC input - // wire [3:0] SDCDatIn; - - // New SDC Command IOBUF connections - wire sd_cmd_i; - wire sd_cmd_reg_o; - wire sd_cmd_reg_t; - - // SD Card Interrupt signal - (* mark_debug = "true" *) wire SDCIntr; - - // New SDC Data IOBUF connections - wire [3:0] sd_dat_i; - wire [3:0] sd_dat_reg_o; - wire sd_dat_reg_t; - - assign GPIOIN = {28'b0, GPI}; + assign GPIOIN = {25'b0, SDCCD, SDCWP, 2'b0, GPI}; assign GPO = GPIOOUT[4:0]; assign ahblite_resetn = peripheral_aresetn; assign cpu_reset = bus_struct_reset; - assign calib = c0_init_calib_complete; + logic [3:0] SDCCSin; + assign SDCCS = SDCCSin[0]; - // SD Card Tristate - /* - IOBUF iobufSDCMD(.T(~SDCCmdOE), // iobuf's T is active low - .I(SDCCmdOut), - .O(SDCCmdIn), - .IO(SDCCmd)); - - genvar i; - generate - for (i = 0; i < 4; i = i + 1) begin - IOBUF iobufSDCDat(.T(1'b1), - .I(1'b0), - .O(SDCDatIn[i]), - .IO(SDCDat[i])); - end - endgenerate - */ - - // IOBUFS for new SDC peripheral - IOBUF IOBUF_cmd (.O(sd_cmd_i), .IO(SDCCmd), .I(sd_cmd_reg_o), .T(sd_cmd_reg_t)); - genvar i; - generate - for (i = 0; i < 4; i = i + 1) begin - IOBUF iobufSDCDat(.T(sd_dat_reg_t), - .I(sd_dat_reg_o[i]), - .O(sd_dat_i[i]), - .IO(SDCDat[i]) ); - end - endgenerate - - // IOBUF IOBUF_dat0 (.O(sd_dat_i[0]), .IO(sdio_dat[0]), .I(sd_dat_reg_o[0]), .T(sd_dat_reg_t)); - // IOBUF IOBUF_dat1 (.O(sd_dat_i[1]), .IO(sdio_dat[1]), .I(sd_dat_reg_o[1]), .T(sd_dat_reg_t)); - // IOBUF IOBUF_dat2 (.O(sd_dat_i[2]), .IO(sdio_dat[2]), .I(sd_dat_reg_o[2]), .T(sd_dat_reg_t)); - // IOBUF IOBUF_dat3 (.O(sd_dat_i[3]), .IO(sdio_dat[3]), .I(sd_dat_reg_o[3]), .T(sd_dat_reg_t)); - - - // reset controller XILINX IP - xlnx_proc_sys_reset xlnx_proc_sys_reset_0 + sysrst sysrst (.slowest_sync_clk(CPUCLK), .ext_reset_in(c0_ddr4_ui_clk_sync_rst), .aux_reset_in(south_rst), @@ -486,58 +207,21 @@ module fpgaTop `include "parameter-defs.vh" + // Wally wallypipelinedsoc #(P) wallypipelinedsoc(.clk(CPUCLK), .reset_ext(bus_struct_reset), .reset(), .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, - .HSELEXTSDC, .HCLK(HCLKOpen), .HRESETn(HRESETnOpen), + .HCLK(HCLKOpen), .HRESETn(HRESETnOpen), .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, - .UARTSin, .UARTSout, .SDCIntr); - - - // RT and JP: FIXME add sdc interrupt and HSELEXTSDC, remove old sdc after the new sdc ahb version is implemented - // wallypipelinedsocwrapper wallypipelinedsocwrapper - // (.clk(CPUCLK), - // .reset_ext(bus_struct_reset), - // // bus interface - // .HRDATAEXT(HRDATAEXT), - // .HREADYEXT(HREADYEXT), - // .HRESPEXT(HRESPEXT), - // .HSELEXT(HSELEXT), - // .HSELEXTSDC(HSELEXTSDC), - // .HCLK(HCLKOpen), // open - // .HRESETn(HRESETnOpen), // open - // .HADDR(HADDR), - // .HWDATA(HWDATA), - // .HWRITE(HWRITE), - // .HSIZE(HSIZE), - // .HBURST(HBURST), - // .HPROT(HPROT), - // .HTRANS(HTRANS), - // .HMASTLOCK(HMASTLOCK), - // .HREADY(HREADY), - // // GPIO - // .GPIOIN(GPIOIN), - // .GPIOOUT(GPIOOUT), - // .GPIOEN(GPIOEN), - // // UART - // .UARTSin(UARTSin), - // .UARTSout(UARTSout), - // .SDCIntr(SDCIntr) - // // SD Card - // /*.SDCDatIn(SDCDatIn), - // .SDCCmdIn(SDCCmdIn), - // .SDCCmdOut(SDCCmdOut), - // .SDCCmdOE(SDCCmdOE), - // .SDCCLK(SDCCLK));*/ - // ); + .UARTSin, .UARTSout, .SDCIn, .SDCCmd, .SDCCS(SDCCSin), .SDCCLK, .ExternalStall(RVVIStall)); // ahb lite to axi bridge - xlnx_ahblite_axi_bridge xlnx_ahblite_axi_bridge_0 + ahbaxibridge ahbaxibridge (.s_ahb_hclk(CPUCLK), .s_ahb_hresetn(peripheral_aresetn), - .s_ahb_hsel(HSELEXT | HSELEXTSDC), + .s_ahb_hsel(HSELEXT), .s_ahb_haddr(HADDR), .s_ahb_hprot(HPROT), .s_ahb_htrans(HTRANS), @@ -585,431 +269,48 @@ module fpgaTop .m_axi_rlast(m_axi_rlast), .m_axi_rready(m_axi_rready)); - // AXI Crossbar for arbitrating the SDC and CPU -------------- - xlnx_axi_crossbar xlnx_axi_crossbar_0 - (.aclk(CPUCLK), - .aresetn(peripheral_aresetn), - - // Connect Masters - .s_axi_awid({4'b1000, m_axi_awid}), - .s_axi_awaddr({m01_axi_awaddr, m_axi_awaddr}), - .s_axi_awlen({m01_axi_awlen, m_axi_awlen}), - .s_axi_awsize({m01_axi_awsize, m_axi_awsize}), - .s_axi_awburst({m01_axi_awburst, m_axi_awburst}), - .s_axi_awlock({m01_axi_awlock, m_axi_awlock}), - .s_axi_awcache({m01_axi_awcache, m_axi_awcache}), - .s_axi_awprot({m01_axi_awprot, m_axi_awprot}), - .s_axi_awqos(8'b0), - .s_axi_awvalid({m01_axi_awvalid, m_axi_awvalid}), - .s_axi_awready({m01_axi_awready, m_axi_awready}), - .s_axi_wdata({m01_axi_wdata, m_axi_wdata}), - .s_axi_wstrb({m01_axi_wstrb, m_axi_wstrb}), - .s_axi_wlast({m01_axi_wlast, m_axi_wlast}), - .s_axi_wvalid({m01_axi_wvalid, m_axi_wvalid}), - .s_axi_wready({m01_axi_wready, m_axi_wready}), - .s_axi_bid({m01_axi_bid, m_axi_bid}), - .s_axi_bresp({m01_axi_bresp, m_axi_bresp}), - .s_axi_bvalid({m01_axi_bvalid, m_axi_bvalid}), - .s_axi_bready({m01_axi_bready, m_axi_bready}), - .s_axi_arid({4'b1000, m_axi_arid}), - .s_axi_araddr({m01_axi_araddr, m_axi_araddr}), - .s_axi_arlen({m01_axi_arlen, m_axi_arlen}), - .s_axi_arsize({m01_axi_arsize, m_axi_arsize}), - .s_axi_arburst({m01_axi_arburst, m_axi_arburst}), - .s_axi_arlock({m01_axi_arlock, m_axi_arlock}), - .s_axi_arcache({m01_axi_arcache, m_axi_arcache}), - .s_axi_arprot({m01_axi_arprot, m_axi_arprot}), - .s_axi_arqos(8'b0), - .s_axi_arvalid({m01_axi_arvalid, m_axi_arvalid}), - .s_axi_arready({m01_axi_arready, m_axi_arready}), - .s_axi_rid({m01_axi_rid, m_axi_rid}), - .s_axi_rdata({m01_axi_rdata, m_axi_rdata}), - .s_axi_rresp({m01_axi_rresp, m_axi_rresp}), - .s_axi_rlast({m01_axi_rlast, m_axi_rlast}), - .s_axi_rvalid({m01_axi_rvalid, m_axi_rvalid}), - .s_axi_rready({m01_axi_rready, m_axi_rready}), - - // Connect Slaves - .m_axi_awid({s01_axi_awid, s00_axi_awid}), - .m_axi_awlen({s01_axi_awlen, s00_axi_awlen}), - .m_axi_awsize({s01_axi_awsize, s00_axi_awsize}), - .m_axi_awburst({s01_axi_awburst, s00_axi_awburst}), - .m_axi_awcache({s01_axi_awcache, s00_axi_awcache}), - .m_axi_awaddr({s01_axi_awaddr, s00_axi_awaddr}), - .m_axi_awprot({s01_axi_awprot, s00_axi_awprot}), - .m_axi_awregion({s01_axi_awregion, s00_axi_awregion}), - .m_axi_awqos({s01_axi_awqos, s00_axi_awqos}), - .m_axi_awvalid({s01_axi_awvalid, s00_axi_awvalid}), - .m_axi_awready({s01_axi_awready, s00_axi_awready}), - .m_axi_awlock({s01_axi_awlock, s00_axi_awlock}), - .m_axi_wdata({s01_axi_wdata, s00_axi_wdata}), - .m_axi_wstrb({s01_axi_wstrb, s00_axi_wstrb}), - .m_axi_wlast({s01_axi_wlast, s00_axi_wlast}), - .m_axi_wvalid({s01_axi_wvalid, s00_axi_wvalid}), - .m_axi_wready({s01_axi_wready, s00_axi_wready}), - .m_axi_bid({4'b1000, s00_axi_bid}), - .m_axi_bresp({s01_axi_bresp, s00_axi_bresp}), - .m_axi_bvalid({s01_axi_bvalid, s00_axi_bvalid}), - .m_axi_bready({s01_axi_bready, s00_axi_bready}), - .m_axi_arid({s01_axi_arid, s00_axi_arid}), - .m_axi_arlen({s01_axi_arlen, s00_axi_arlen}), - .m_axi_arsize({s01_axi_arsize, s00_axi_arsize}), - .m_axi_arburst({s01_axi_arburst, s00_axi_arburst}), - .m_axi_arprot({s01_axi_arprot, s00_axi_arprot}), - .m_axi_arregion({s01_axi_arregion, s00_axi_arregion}), - .m_axi_arqos({s01_axi_arqos, s00_axi_arqos}), - .m_axi_arcache({s01_axi_arcache, s00_axi_arcache}), - .m_axi_arvalid({s01_axi_arvalid, s00_axi_arvalid}), - .m_axi_araddr({s01_axi_araddr, s00_axi_araddr}), - .m_axi_arlock({s01_axi_arlock, s00_axi_arlock}), - .m_axi_arready({s01_axi_arready, s00_axi_arready}), - .m_axi_rid({4'b1000, s00_axi_rid}), - .m_axi_rdata({s01_axi_rdata, s00_axi_rdata}), - .m_axi_rresp({s01_axi_rresp, s00_axi_rresp}), - .m_axi_rvalid({s01_axi_rvalid, s00_axi_rvalid}), - .m_axi_rlast({s01_axi_rlast, s00_axi_rlast}), - .m_axi_rready({s01_axi_rready, s00_axi_rready}) - ); - - // ----------------------------------------------------- - - // SDC Implementation ---------------------------------- - // - // The SDC peripheral from Eugene Tarassov takes in an AXI4Lite - // interface and outputs an AXI4 interface. In order to convert from - // one to the other, we use these dwidth converters to make sure the - // bit widths match the rest of the bus. - - xlnx_axi_dwidth_conv_64to32 axi_conv_down - (.s_axi_aclk(CPUCLK), - .s_axi_aresetn(peripheral_aresetn), - - // Slave interface - .s_axi_awaddr(s01_axi_awaddr), - .s_axi_awlen(s01_axi_awlen), - .s_axi_awsize(s01_axi_awsize), - .s_axi_awburst(s01_axi_awburst), - .s_axi_awlock(s01_axi_awlock), - .s_axi_awcache(s01_axi_awcache), - .s_axi_awprot(s01_axi_awprot), - .s_axi_awregion(s01_axi_awregion), - .s_axi_awqos(4'b0), - .s_axi_awvalid(s01_axi_awvalid), - .s_axi_awready(s01_axi_awready), - .s_axi_wdata(s01_axi_wdata), - .s_axi_wstrb(s01_axi_wstrb), - .s_axi_wlast(s01_axi_wlast), - .s_axi_wvalid(s01_axi_wvalid), - .s_axi_wready(s01_axi_wready), - .s_axi_bresp(s01_axi_bresp), - .s_axi_bvalid(s01_axi_bvalid), - .s_axi_bready(s01_axi_bready), - .s_axi_araddr(s01_axi_araddr), - .s_axi_arlen(s01_axi_arlen), - .s_axi_arsize(s01_axi_arsize), - .s_axi_arburst(s01_axi_arburst), - .s_axi_arlock(s01_axi_arlock), - .s_axi_arcache(s01_axi_arcache), - .s_axi_arprot(s01_axi_arprot), - .s_axi_arregion(s01_axi_arregion), - .s_axi_arqos(4'b0), - .s_axi_arvalid(s01_axi_arvalid), - .s_axi_arready(s01_axi_arready), - .s_axi_rdata(s01_axi_rdata), - .s_axi_rresp(s01_axi_rresp), - .s_axi_rlast(s01_axi_rlast), - .s_axi_rvalid(s01_axi_rvalid), - .s_axi_rready(s01_axi_rready), - - // Master interface - .m_axi_awaddr(axi4in_axi_awaddr), - .m_axi_awlen(axi4in_axi_awlen), - .m_axi_awsize(axi4in_axi_awsize), - .m_axi_awburst(axi4in_axi_awburst), - .m_axi_awlock(axi4in_axi_awlock), - .m_axi_awcache(axi4in_axi_awcache), - .m_axi_awprot(axi4in_axi_awprot), - .m_axi_awregion(axi4in_axi_awregion), - .m_axi_awqos(axi4in_axi_awqos), - .m_axi_awvalid(axi4in_axi_awvalid), - .m_axi_awready(axi4in_axi_awready), - .m_axi_wdata(axi4in_axi_wdata), - .m_axi_wstrb(axi4in_axi_wstrb), - .m_axi_wlast(axi4in_axi_wlast), - .m_axi_wvalid(axi4in_axi_wvalid), - .m_axi_wready(axi4in_axi_wready), - .m_axi_bresp(axi4in_axi_bresp), - .m_axi_bvalid(axi4in_axi_bvalid), - .m_axi_bready(axi4in_axi_bready), - .m_axi_araddr(axi4in_axi_araddr), - .m_axi_arlen(axi4in_axi_arlen), - .m_axi_arsize(axi4in_axi_arsize), - .m_axi_arburst(axi4in_axi_arburst), - .m_axi_arlock(axi4in_axi_arlock), - .m_axi_arcache(axi4in_axi_arcache), - .m_axi_arprot(axi4in_axi_arprot), - .m_axi_arregion(axi4in_axi_arregion), - .m_axi_arqos(axi4in_axi_arqos), - .m_axi_arvalid(axi4in_axi_arvalid), - .m_axi_arready(axi4in_axi_arready), - .m_axi_rdata(axi4in_axi_rdata), - .m_axi_rresp(axi4in_axi_rresp), - .m_axi_rlast(axi4in_axi_rlast), - .m_axi_rvalid(axi4in_axi_rvalid), - .m_axi_rready(axi4in_axi_rready) - ); - - xlnx_axi_prtcl_conv axi4tolite - (.aclk(CPUCLK), - .aresetn(peripheral_aresetn), - - // AXI4 In - .s_axi_awaddr(axi4in_axi_awaddr), - .s_axi_awlen(axi4in_axi_awlen), - .s_axi_awsize(axi4in_axi_awsize), - .s_axi_awburst(axi4in_axi_awburst), - .s_axi_awlock(axi4in_axi_awlock), - .s_axi_awcache(axi4in_axi_awcache), - .s_axi_awprot(axi4in_axi_awprot), - .s_axi_awregion(axi4in_axi_awregion), - .s_axi_awqos(axi4in_axi_awqos), - .s_axi_awvalid(axi4in_axi_awvalid), - .s_axi_awready(axi4in_axi_awready), - .s_axi_wdata(axi4in_axi_wdata), - .s_axi_wstrb(axi4in_axi_wstrb), - .s_axi_wlast(axi4in_axi_wlast), - .s_axi_wvalid(axi4in_axi_wvalid), - .s_axi_wready(axi4in_axi_wready), - .s_axi_bresp(axi4in_axi_bresp), - .s_axi_bvalid(axi4in_axi_bvalid), - .s_axi_bready(axi4in_axi_bready), - .s_axi_araddr(axi4in_axi_araddr), - .s_axi_arlen(axi4in_axi_arlen), - .s_axi_arsize(axi4in_axi_arsize), - .s_axi_arburst(axi4in_axi_arburst), - .s_axi_arlock(axi4in_axi_arlock), - .s_axi_arcache(axi4in_axi_arcache), - .s_axi_arprot(axi4in_axi_arprot), - .s_axi_arregion(axi4in_axi_arregion), - .s_axi_arqos(axi4in_axi_arqos), - .s_axi_arvalid(axi4in_axi_arvalid), - .s_axi_arready(axi4in_axi_arready), - .s_axi_rdata(axi4in_axi_rdata), - .s_axi_rresp(axi4in_axi_rresp), - .s_axi_rlast(axi4in_axi_rlast), - .s_axi_rvalid(axi4in_axi_rvalid), - .s_axi_rready(axi4in_axi_rready), - - // AXI4Lite Out - .m_axi_awaddr(SDCin_axi_awaddr), - .m_axi_awprot(SDCin_axi_awprot), - .m_axi_awvalid(SDCin_axi_awvalid), - .m_axi_awready(SDCin_axi_awready), - .m_axi_wdata(SDCin_axi_wdata), - .m_axi_wstrb(SDCin_axi_wstrb), - .m_axi_wvalid(SDCin_axi_wvalid), - .m_axi_wready(SDCin_axi_wready), - .m_axi_bresp(SDCin_axi_bresp), - .m_axi_bvalid(SDCin_axi_bvalid), - .m_axi_bready(SDCin_axi_bready), - .m_axi_araddr(SDCin_axi_araddr), - .m_axi_arprot(SDCin_axi_arprot), - .m_axi_arvalid(SDCin_axi_arvalid), - .m_axi_arready(SDCin_axi_arready), - .m_axi_rdata(SDCin_axi_rdata), - .m_axi_rresp(SDCin_axi_rresp), - .m_axi_rvalid(SDCin_axi_rvalid), - .m_axi_rready(SDCin_axi_rready) - - ); - - - sdc_controller axiSDC - (.clock(CPUCLK), - .async_resetn(peripheral_aresetn), - - // Slave Interface - .s_axi_awaddr({8'b0, SDCin_axi_awaddr[7:0]}), - .s_axi_awvalid(SDCin_axi_awvalid), - .s_axi_awready(SDCin_axi_awready), - .s_axi_wdata(SDCin_axi_wdata), - .s_axi_wvalid(SDCin_axi_wvalid), - .s_axi_wready(SDCin_axi_wready), - .s_axi_bresp(SDCin_axi_bresp), - .s_axi_bvalid(SDCin_axi_bvalid), - .s_axi_bready(SDCin_axi_bready), - .s_axi_araddr({8'b0, SDCin_axi_araddr[7:0]}), - .s_axi_arvalid(SDCin_axi_arvalid), - .s_axi_arready(SDCin_axi_arready), - .s_axi_rdata(SDCin_axi_rdata), - .s_axi_rresp(SDCin_axi_rresp), - .s_axi_rvalid(SDCin_axi_rvalid), - .s_axi_rready(SDCin_axi_rready), - - // Master Interface - .m_axi_awaddr(SDCout_axi_awaddr), - .m_axi_awlen(SDCout_axi_awlen), - .m_axi_awvalid(SDCout_axi_awvalid), - .m_axi_awready(SDCout_axi_awready), - .m_axi_wdata(SDCout_axi_wdata), - .m_axi_wlast(SDCout_axi_wlast), - .m_axi_wvalid(SDCout_axi_wvalid), - .m_axi_wready(SDCout_axi_wready), - .m_axi_bresp(SDCout_axi_bresp), - .m_axi_bvalid(SDCout_axi_bvalid), - .m_axi_bready(SDCout_axi_bready), - .m_axi_araddr(SDCout_axi_araddr), - .m_axi_arlen(SDCout_axi_arlen), - .m_axi_arvalid(SDCout_axi_arvalid), - .m_axi_arready(SDCout_axi_arready), - .m_axi_rdata(SDCout_axi_rdata), - .m_axi_rlast(SDCout_axi_rlast), - .m_axi_rresp(SDCout_axi_rresp), - .m_axi_rvalid(SDCout_axi_rvalid), - .m_axi_rready(SDCout_axi_rready), - - // SDC interface - //.sdio_cmd(1'b0), - //.sdio_dat(4'b0), - //.sdio_cd(1'b0) - - .sd_dat_reg_t(sd_dat_reg_t), - .sd_dat_reg_o(sd_dat_reg_o), - .sd_dat_i(sd_dat_i), - - .sd_cmd_reg_t(sd_cmd_reg_t), - .sd_cmd_reg_o(sd_cmd_reg_o), - .sd_cmd_i(sd_cmd_i), - - .sdio_clk(SDCCLK), - .sdio_cd(SDCCD), - - .interrupt(SDCIntr) - ); - - xlnx_axi_dwidth_conv_32to64 axi_conv_up - (.s_axi_aclk(CPUCLK), - .s_axi_aresetn(peripheral_aresetn), - - // Slave interface - .s_axi_awaddr(SDCout_axi_awaddr), - .s_axi_awlen(SDCout_axi_awlen), - .s_axi_awsize(3'b010), - .s_axi_awburst(2'b01), - .s_axi_awlock(1'b0), - .s_axi_awcache(4'b0), - .s_axi_awprot(3'b0), - .s_axi_awregion(4'b0), - .s_axi_awqos(4'b0), - .s_axi_awvalid(SDCout_axi_awvalid), - .s_axi_awready(SDCout_axi_awready), - .s_axi_wdata(SDCout_axi_wdata), - .s_axi_wstrb(8'b11111111), - .s_axi_wlast(SDCout_axi_wlast), - .s_axi_wvalid(SDCout_axi_wvalid), - .s_axi_wready(SDCout_axi_wready), - .s_axi_bresp(SDCout_axi_bresp), - .s_axi_bvalid(SDCout_axi_bvalid), - .s_axi_bready(SDCout_axi_bready), - .s_axi_araddr(SDCout_axi_araddr), - .s_axi_arlen(SDCout_axi_arlen), - .s_axi_arsize(3'b010), - .s_axi_arburst(2'b01), - .s_axi_arlock(1'b0), - .s_axi_arcache(4'b0), - .s_axi_arprot(3'b0), - .s_axi_arregion(4'b0), - .s_axi_arqos(4'b0), - .s_axi_arvalid(SDCout_axi_arvalid), - .s_axi_arready(SDCout_axi_arready), - .s_axi_rdata(SDCout_axi_rdata), - .s_axi_rresp(SDCout_axi_rresp), - .s_axi_rlast(SDCout_axi_rlast), - .s_axi_rvalid(SDCout_axi_rvalid), - .s_axi_rready(SDCout_axi_rready), - - // Master interface - .m_axi_awaddr(m01_axi_awaddr), - .m_axi_awlen(m01_axi_awlen), - .m_axi_awsize(m01_axi_awsize), - .m_axi_awburst(m01_axi_awburst), - .m_axi_awlock(m01_axi_awlock), - .m_axi_awcache(m01_axi_awcache), - .m_axi_awprot(m01_axi_awprot), - .m_axi_awregion(m01_axi_awregion), - .m_axi_awqos(m01_axi_awqos), - .m_axi_awvalid(m01_axi_awvalid), - .m_axi_awready(m01_axi_awready), - .m_axi_wdata(m01_axi_wdata), - .m_axi_wstrb(m01_axi_wstrb), - .m_axi_wlast(m01_axi_wlast), - .m_axi_wvalid(m01_axi_wvalid), - .m_axi_wready(m01_axi_wready), - .m_axi_bresp(m01_axi_bresp), - .m_axi_bvalid(m01_axi_bvalid), - .m_axi_bready(m01_axi_bready), - .m_axi_araddr(m01_axi_araddr), - .m_axi_arlen(m01_axi_arlen), - .m_axi_arsize(m01_axi_arsize), - .m_axi_arburst(m01_axi_arburst), - .m_axi_arlock(m01_axi_arlock), - .m_axi_arcache(m01_axi_arcache), - .m_axi_arprot(m01_axi_arprot), - .m_axi_arregion(m01_axi_arregion), - .m_axi_arqos(m01_axi_arqos), - .m_axi_arvalid(m01_axi_arvalid), - .m_axi_arready(m01_axi_arready), - .m_axi_rdata(m01_axi_rdata), - .m_axi_rresp(m01_axi_rresp), - .m_axi_rlast(m01_axi_rlast), - .m_axi_rvalid(m01_axi_rvalid), - .m_axi_rready(m01_axi_rready) - ); - - // End SDC signals -------------------------------------------- - - xlnx_axi_clock_converter xlnx_axi_clock_converter_0 + clkconverter clkconverter (.s_axi_aclk(CPUCLK), .s_axi_aresetn(peripheral_aresetn), - .s_axi_awid(s00_axi_awid), - .s_axi_awlen(s00_axi_awlen), - .s_axi_awsize(s00_axi_awsize), - .s_axi_awburst(s00_axi_awburst), - .s_axi_awcache(s00_axi_awcache), - .s_axi_awaddr(s00_axi_awaddr[30:0] ), - .s_axi_awprot(s00_axi_awprot), + .s_axi_awid(m_axi_awid), + .s_axi_awlen(m_axi_awlen), + .s_axi_awsize(m_axi_awsize), + .s_axi_awburst(m_axi_awburst), + .s_axi_awcache(m_axi_awcache), + .s_axi_awaddr(m_axi_awaddr[30:0] ), + .s_axi_awprot(m_axi_awprot), .s_axi_awregion(4'b0), // this could be a bug. bridge does not have these outputs .s_axi_awqos(4'b0), // this could be a bug. bridge does not have these outputs - .s_axi_awvalid(s00_axi_awvalid), - .s_axi_awready(s00_axi_awready), - .s_axi_awlock(s00_axi_awlock), - .s_axi_wdata(s00_axi_wdata), - .s_axi_wstrb(s00_axi_wstrb), - .s_axi_wlast(s00_axi_wlast), - .s_axi_wvalid(s00_axi_wvalid), - .s_axi_wready(s00_axi_wready), - .s_axi_bid(s00_axi_bid), - .s_axi_bresp(s00_axi_bresp), - .s_axi_bvalid(s00_axi_bvalid), - .s_axi_bready(s00_axi_bready), - .s_axi_arid(s00_axi_arid), - .s_axi_arlen(s00_axi_arlen), - .s_axi_arsize(s00_axi_arsize), - .s_axi_arburst(s00_axi_arburst), - .s_axi_arprot(s00_axi_arprot), + .s_axi_awvalid(m_axi_awvalid), + .s_axi_awready(m_axi_awready), + .s_axi_awlock(m_axi_awlock), + .s_axi_wdata(m_axi_wdata), + .s_axi_wstrb(m_axi_wstrb), + .s_axi_wlast(m_axi_wlast), + .s_axi_wvalid(m_axi_wvalid), + .s_axi_wready(m_axi_wready), + .s_axi_bid(m_axi_bid), + .s_axi_bresp(m_axi_bresp), + .s_axi_bvalid(m_axi_bvalid), + .s_axi_bready(m_axi_bready), + .s_axi_arid(m_axi_arid), + .s_axi_arlen(m_axi_arlen), + .s_axi_arsize(m_axi_arsize), + .s_axi_arburst(m_axi_arburst), + .s_axi_arprot(m_axi_arprot), .s_axi_arregion(4'b0), // this could be a bug. bridge does not have these outputs .s_axi_arqos(4'b0), // this could be a bug. bridge does not have these outputs - .s_axi_arcache(s00_axi_arcache), - .s_axi_arvalid(s00_axi_arvalid), - .s_axi_araddr(s00_axi_araddr[30:0]), - .s_axi_arlock(s00_axi_arlock), - .s_axi_arready(s00_axi_arready), - .s_axi_rid(s00_axi_rid), - .s_axi_rdata(s00_axi_rdata), - .s_axi_rresp(s00_axi_rresp), - .s_axi_rvalid(s00_axi_rvalid), - .s_axi_rlast(s00_axi_rlast), - .s_axi_rready(s00_axi_rready), + .s_axi_arcache(m_axi_arcache), + .s_axi_arvalid(m_axi_arvalid), + .s_axi_araddr(m_axi_araddr[30:0]), + .s_axi_arlock(m_axi_arlock), + .s_axi_arready(m_axi_arready), + .s_axi_rid(m_axi_rid), + .s_axi_rdata(m_axi_rdata), + .s_axi_rresp(m_axi_rresp), + .s_axi_rvalid(m_axi_rvalid), + .s_axi_rlast(m_axi_rlast), + .s_axi_rready(m_axi_rready), .m_axi_aclk(BUSCLK), .m_axi_aresetn(~reset), @@ -1053,7 +354,7 @@ module fpgaTop .m_axi_rlast(BUS_axi_rlast), .m_axi_rready(BUS_axi_rready)); - xlnx_ddr4 xlnx_ddr4_c0 + ddr4 ddr4 (.c0_init_calib_complete(c0_init_calib_complete), .dbg_clk(dbg_clk), // open .c0_sys_clk_p(default_250mhz_clk1_0_p), @@ -1122,8 +423,7 @@ module fpgaTop .addn_ui_clkout1(CPUCLK), .addn_ui_clkout2(CLK208)); - - + assign RVVIStall = '0; endmodule diff --git a/fpga/src/fpgaTopArtyA7.sv b/fpga/src/fpgaTopArtyA7.sv index 9133baa25..676d4d9a7 100644 --- a/fpga/src/fpgaTopArtyA7.sv +++ b/fpga/src/fpgaTopArtyA7.sv @@ -29,183 +29,183 @@ import cvw::*; module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) - (input default_100mhz_clk, -(* mark_debug = "true" *) input resetn, - input south_reset, + (input logic default_100mhz_clk, + input logic resetn, + input logic south_reset, // GPIO signals - input [3:0] GPI, - output [4:0] GPO, + input logic [3:0] GPI, + output logic [4:0] GPO, // UART Signals - input UARTSin, - output UARTSout, + input logic UARTSin, + output logic UARTSout, // SDC Signals connecting to an SPI peripheral - input SDCIn, - output SDCCLK, - output SDCCmd, - output SDCCS, - input SDCCD, - input SDCWP, + input logic SDCIn, + output logic SDCCLK, + output logic SDCCmd, + output logic SDCCS, + input logic SDCCD, + input logic SDCWP, /* * Ethernet: 100BASE-T MII */ - output phy_ref_clk, - input phy_rx_clk, - input [3:0] phy_rxd, - input phy_rx_dv, - input phy_rx_er, - input phy_tx_clk, - output [3:0] phy_txd, - output phy_tx_en, - input phy_col, // nc - input phy_crs, // nc - output phy_reset_n, + output logic phy_ref_clk, + input logic phy_rx_clk, + input logic [3:0] phy_rxd, + input logic phy_rx_dv, + input logic phy_rx_er, + input logic phy_tx_clk, + output logic [3:0] phy_txd, + output logic phy_tx_en, + input logic phy_col, // nc + input logic phy_crs, // nc + output logic phy_reset_n, - inout [15:0] ddr3_dq, - inout [1:0] ddr3_dqs_n, - inout [1:0] ddr3_dqs_p, - output [13:0] ddr3_addr, - output [2:0] ddr3_ba, - output ddr3_ras_n, - output ddr3_cas_n, - output ddr3_we_n, - output ddr3_reset_n, - output [0:0] ddr3_ck_p, - output [0:0] ddr3_ck_n, - output [0:0] ddr3_cke, - output [0:0] ddr3_cs_n, - output [1:0] ddr3_dm, - output [0:0] ddr3_odt + inout logic [15:0] ddr3_dq, + inout logic [1:0] ddr3_dqs_n, + inout logic [1:0] ddr3_dqs_p, + output logic [13:0] ddr3_addr, + output logic [2:0] ddr3_ba, + output logic ddr3_ras_n, + output logic ddr3_cas_n, + output logic ddr3_we_n, + output logic ddr3_reset_n, + output logic [0:0] ddr3_ck_p, + output logic [0:0] ddr3_ck_n, + output logic [0:0] ddr3_cke, + output logic [0:0] ddr3_cs_n, + output logic [1:0] ddr3_dm, + output logic [0:0] ddr3_odt ); // MMCM Signals - wire CPUCLK; - wire c0_ddr4_ui_clk_sync_rst; - wire bus_struct_reset; - wire peripheral_reset; - wire interconnect_aresetn; - wire peripheral_aresetn; - wire mb_reset; + logic CPUCLK; + logic c0_ddr4_ui_clk_sync_rst; + logic bus_struct_reset; + logic peripheral_reset; + logic interconnect_aresetn; + logic peripheral_aresetn; + logic mb_reset; // AHB Signals from Wally - wire HCLKOpen; - wire HRESETnOpen; - wire [63:0] HRDATAEXT; - wire HREADYEXT; - wire HRESPEXT; - wire HSELEXT; - wire [55:0] HADDR; - wire [63:0] HWDATA; - wire [64/8-1:0] HWSTRB; - wire HWRITE; - wire [2:0] HSIZE; - wire [2:0] HBURST; - wire [1:0] HTRANS; - wire HREADY; - wire [3:0] HPROT; - wire HMASTLOCK; + logic HCLKOpen; + logic HRESETnOpen; + logic [63:0] HRDATAEXT; + logic HREADYEXT; + logic HRESPEXT; + logic HSELEXT; + logic [55:0] HADDR; + logic [63:0] HWDATA; + logic [64/8-1:0] HWSTRB; + logic HWRITE; + logic [2:0] HSIZE; + logic [2:0] HBURST; + logic [1:0] HTRANS; + logic HREADY; + logic [3:0] HPROT; + logic HMASTLOCK; // GPIO Signals - wire [31:0] GPIOIN, GPIOOUT, GPIOEN; + logic [31:0] GPIOIN, GPIOOUT, GPIOEN; // AHB to AXI Bridge Signals - wire [3:0] m_axi_awid; - wire [7:0] m_axi_awlen; - wire [2:0] m_axi_awsize; - wire [1:0] m_axi_awburst; - wire [3:0] m_axi_awcache; - wire [31:0] m_axi_awaddr; - wire [2:0] m_axi_awprot; - wire m_axi_awvalid; - wire m_axi_awready; - wire m_axi_awlock; - wire [63:0] m_axi_wdata; - wire [7:0] m_axi_wstrb; - wire m_axi_wlast; - wire m_axi_wvalid; - wire m_axi_wready; - wire [3:0] m_axi_bid; - wire [1:0] m_axi_bresp; - wire m_axi_bvalid; - wire m_axi_bready; - wire [3:0] m_axi_arid; - wire [7:0] m_axi_arlen; - wire [2:0] m_axi_arsize; - wire [1:0] m_axi_arburst; - wire [2:0] m_axi_arprot; - wire [3:0] m_axi_arcache; - wire m_axi_arvalid; - wire [31:0] m_axi_araddr; - wire m_axi_arlock; - wire m_axi_arready; - wire [3:0] m_axi_rid; - wire [63:0] m_axi_rdata; - wire [1:0] m_axi_rresp; - wire m_axi_rvalid; - wire m_axi_rlast; - wire m_axi_rready; + logic [3:0] m_axi_awid; + logic [7:0] m_axi_awlen; + logic [2:0] m_axi_awsize; + logic [1:0] m_axi_awburst; + logic [3:0] m_axi_awcache; + logic [31:0] m_axi_awaddr; + logic [2:0] m_axi_awprot; + logic m_axi_awvalid; + logic m_axi_awready; + logic m_axi_awlock; + logic [63:0] m_axi_wdata; + logic [7:0] m_axi_wstrb; + logic m_axi_wlast; + logic m_axi_wvalid; + logic m_axi_wready; + logic [3:0] m_axi_bid; + logic [1:0] m_axi_bresp; + logic m_axi_bvalid; + logic m_axi_bready; + logic [3:0] m_axi_arid; + logic [7:0] m_axi_arlen; + logic [2:0] m_axi_arsize; + logic [1:0] m_axi_arburst; + logic [2:0] m_axi_arprot; + logic [3:0] m_axi_arcache; + logic m_axi_arvalid; + logic [31:0] m_axi_araddr; + logic m_axi_arlock; + logic m_axi_arready; + logic [3:0] m_axi_rid; + logic [63:0] m_axi_rdata; + logic [1:0] m_axi_rresp; + logic m_axi_rvalid; + logic m_axi_rlast; + logic m_axi_rready; // AXI Signals going out of Clock Converter - wire [3:0] BUS_axi_arregion; - wire [3:0] BUS_axi_arqos; - wire [3:0] BUS_axi_awregion; - wire [3:0] BUS_axi_awqos; - wire [3:0] BUS_axi_awid; - wire [7:0] BUS_axi_awlen; - wire [2:0] BUS_axi_awsize; - wire [1:0] BUS_axi_awburst; - wire [3:0] BUS_axi_awcache; - wire [31:0] BUS_axi_awaddr; - wire [2:0] BUS_axi_awprot; - wire BUS_axi_awvalid; - wire BUS_axi_awready; - wire BUS_axi_awlock; - wire [63:0] BUS_axi_wdata; - wire [7:0] BUS_axi_wstrb; - wire BUS_axi_wlast; - wire BUS_axi_wvalid; - wire BUS_axi_wready; - wire [3:0] BUS_axi_bid; - wire [1:0] BUS_axi_bresp; - wire BUS_axi_bvalid; - wire BUS_axi_bready; - wire [3:0] BUS_axi_arid; - wire [7:0] BUS_axi_arlen; - wire [2:0] BUS_axi_arsize; - wire [1:0] BUS_axi_arburst; - wire [2:0] BUS_axi_arprot; - wire [3:0] BUS_axi_arcache; - wire BUS_axi_arvalid; - wire [31:0] BUS_axi_araddr; - wire BUS_axi_arlock; - wire BUS_axi_arready; - wire [3:0] BUS_axi_rid; - wire [63:0] BUS_axi_rdata; - wire [1:0] BUS_axi_rresp; - wire BUS_axi_rvalid; - wire BUS_axi_rlast; - wire BUS_axi_rready; + logic [3:0] BUS_axi_arregion; + logic [3:0] BUS_axi_arqos; + logic [3:0] BUS_axi_awregion; + logic [3:0] BUS_axi_awqos; + logic [3:0] BUS_axi_awid; + logic [7:0] BUS_axi_awlen; + logic [2:0] BUS_axi_awsize; + logic [1:0] BUS_axi_awburst; + logic [3:0] BUS_axi_awcache; + logic [31:0] BUS_axi_awaddr; + logic [2:0] BUS_axi_awprot; + logic BUS_axi_awvalid; + logic BUS_axi_awready; + logic BUS_axi_awlock; + logic [63:0] BUS_axi_wdata; + logic [7:0] BUS_axi_wstrb; + logic BUS_axi_wlast; + logic BUS_axi_wvalid; + logic BUS_axi_wready; + logic [3:0] BUS_axi_bid; + logic [1:0] BUS_axi_bresp; + logic BUS_axi_bvalid; + logic BUS_axi_bready; + logic [3:0] BUS_axi_arid; + logic [7:0] BUS_axi_arlen; + logic [2:0] BUS_axi_arsize; + logic [1:0] BUS_axi_arburst; + logic [2:0] BUS_axi_arprot; + logic [3:0] BUS_axi_arcache; + logic BUS_axi_arvalid; + logic [31:0] BUS_axi_araddr; + logic BUS_axi_arlock; + logic BUS_axi_arready; + logic [3:0] BUS_axi_rid; + logic [63:0] BUS_axi_rdata; + logic [1:0] BUS_axi_rresp; + logic BUS_axi_rvalid; + logic BUS_axi_rlast; + logic BUS_axi_rready; - wire BUSCLK; - wire sdio_reset_open; + logic BUSCLK; + logic sdio_reset_open; - wire c0_init_calib_complete; - wire dbg_clk; - wire [511 : 0] dbg_bus; - wire ui_clk_sync_rst; + logic c0_init_calib_complete; + logic dbg_clk; + logic [511 : 0] dbg_bus; + logic ui_clk_sync_rst; - wire CLK208; - wire clk167; - wire clk200; + logic CLK208; + logic clk167; + logic clk200; - wire app_sr_active; - wire app_ref_ack; - wire app_zq_ack; - wire mmcm_locked; - wire [11:0] device_temp; - wire mmcm1_locked; + logic app_sr_active; + logic app_ref_ack; + logic app_zq_ack; + logic mmcm_locked; + logic [11:0] device_temp; + logic mmcm1_locked; (* mark_debug = "true" *) logic RVVIStall; @@ -225,7 +225,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) // 2. a second clock which is 200 MHz // Wally requires a slower clock. At this point I don't know what speed the atrix 7 will run so I'm initially targetting 25Mhz. // the mig will output a clock at 1/4 the sys clock or 41Mhz which might work with wally so we may be able to simplify the logic a lot. - xlnx_mmcm xln_mmcm(.clk_out1(clk167), + mmcm mmcm(.clk_out1(clk167), .clk_out2(clk200), .clk_out3(CPUCLK), .clk_out4(phy_ref_clk), @@ -236,7 +236,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) // reset controller XILINX IP - xlnx_proc_sys_reset xlnx_proc_sys_reset_0 + sysrst sysrst (.slowest_sync_clk(CPUCLK), .ext_reset_in(1'b0), .aux_reset_in(south_reset), @@ -262,7 +262,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) // ahb lite to axi bridge - xlnx_ahblite_axi_bridge xlnx_ahblite_axi_bridge_0 + ahbaxibridge ahbaxibridge (.s_ahb_hclk(CPUCLK), .s_ahb_hresetn(peripheral_aresetn), .s_ahb_hsel(HSELEXT), @@ -314,7 +314,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) .m_axi_rready(m_axi_rready)); // AXI Clock Converter - xlnx_axi_clock_converter xlnx_axi_clock_converter_0 + clkconverter clkconverter (.s_axi_aclk(CPUCLK), .s_axi_aresetn(peripheral_aresetn), .s_axi_awid(m_axi_awid), @@ -400,7 +400,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) .m_axi_rready(BUS_axi_rready)); // DDR3 Controller - xlnx_ddr3 xlnx_ddr3_c0 + ddr3 ddr3 ( // ddr3 I/O .ddr3_dq(ddr3_dq), diff --git a/fpga/src/wallypipelinedsocwrapper.sv b/fpga/src/wallypipelinedsocwrapper.sv index 40a2a81b3..a1e907913 100644 --- a/fpga/src/wallypipelinedsocwrapper.sv +++ b/fpga/src/wallypipelinedsocwrapper.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // wallypipelinedsocwrapper.sv // -// Written: Ross Thompson ross1728@gmail.com 16 June 2023 +// Written: Rose Thompson ross1728@gmail.com 16 June 2023 // Modified: // // Purpose: A wrapper to set parameters. Vivado cannot set the top level parameters because it only supports verilog, diff --git a/fpga/zsbl/boot.c b/fpga/zsbl/boot.c index e98eda2c1..d9a824a49 100644 --- a/fpga/zsbl/boot.c +++ b/fpga/zsbl/boot.c @@ -52,6 +52,42 @@ when 8 bytes are transferred */ +// crc16 table to reduce byte processing time +static const uint16_t crctable[256] = { + 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, + 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, + 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, + 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, + 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, + 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, + 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4, + 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, + 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, + 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, + 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12, + 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, + 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41, + 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49, + 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70, + 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, + 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f, + 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, + 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, + 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256, + 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, + 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, + 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c, + 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, + 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, + 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3, + 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, + 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92, + 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, + 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1, + 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, + 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0 +}; + int disk_read(BYTE * buf, LBA_t sector, UINT count) { uint64_t r; UINT i, j; @@ -86,6 +122,7 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) { for (i = 0; i < count; i++) { uint16_t crc, crc_exp; uint64_t n = 0; + uint64_t readCount = 0; // Wait for data token while((r = spi_dummy()) != SD_DATA_TOKEN); @@ -98,21 +135,45 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) { /* crc = crc16(crc, x); */ /* } while (--n > 0); */ - n = 512/8; - do { - // Send 8 dummy bytes (fifo should be empty) - for (j = 0; j < 8; j++) { + /* n = 512/8; */ + /* do { */ + /* // Send 8 dummy bytes (fifo should be empty) */ + /* for (j = 0; j < 8; j++) { */ + /* spi_sendbyte(0xff); */ + /* } */ + + /* // Reset counter. Process bytes AS THEY COME IN. */ + /* for (j = 0; j < 8; j++) { */ + /* while (!(read_reg(SPI_IP) & 2)) {} */ + /* uint8_t x = spi_readbyte(); */ + /* *p++ = x; */ + /* // crc = crc16(crc, x); */ + /* crc = ((crc << 8) ^ crctable[x ^ (crc >> 8)]) & 0xffff; */ + /* } */ + /* } while(--n > 0); */ + + n = 512; + // Initially fill the transmit fifo + for (j = 0; j < 8; j++) { + spi_sendbyte(0xff); + } + + + while (n > 0) { + // Wait for bytes to be received + while (!(read_reg(SPI_IP) & 2)) {} + // Read byte + uint8_t x = spi_readbyte(); + // Send another dummy byte + if (n > 8) { spi_sendbyte(0xff); } - - // Reset counter. Process bytes AS THEY COME IN. - for (j = 0; j < 8; j++) { - while (!(read_reg(SPI_IP) & 2)) {} - uint8_t x = spi_readbyte(); - *p++ = x; - crc = crc16(crc, x); - } - } while(--n > 0); + // Place received byte into memory + *p++ = x; + // Update CRC16 with fast table based method + crc = ((crc << 8) ^ crctable[x ^ (crc >> 8)]) & 0xffff; + n = n - 1; + } // Read CRC16 and check crc_exp = ((uint16_t)spi_dummy() << 8); @@ -153,7 +214,7 @@ void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) { int ret = 0; // Initialize UART for messages - init_uart(20000000, 115200); + init_uart(SYSTEMCLOCK, 115200); // Print the wally banner print_uart(BANNER); diff --git a/fpga/zsbl/spi.h b/fpga/zsbl/spi.h index d2bf1191c..f9e88fa6d 100644 --- a/fpga/zsbl/spi.h +++ b/fpga/zsbl/spi.h @@ -1,3 +1,32 @@ +/////////////////////////////////////////////////////////////////////// +// spi.h +// +// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024 +// +// Purpose: Header file for interfaceing with the SPI peripheral +// +// +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the +// “License”); you may not use this file except in compliance with the +// License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an “AS IS” BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +// implied. See the License for the specific language governing +// permissions and limitations under the License. +/////////////////////////////////////////////////////////////////////// + #pragma once #ifndef SPI_HEADER #define SPI_HEADER diff --git a/linux/devicetree/wally-artya7.dts b/linux/devicetree/wally-artya7.dts index 99b8ff00d..5b0580695 100644 --- a/linux/devicetree/wally-artya7.dts +++ b/linux/devicetree/wally-artya7.dts @@ -21,8 +21,8 @@ cpus { #address-cells = <0x01>; #size-cells = <0x00>; - clock-frequency = <0x1312D00>; - timebase-frequency = <0x1312D00>; + clock-frequency = <0x17D7840>; + timebase-frequency = <0x17D7840>; cpu@0 { phandle = <0x01>; @@ -54,7 +54,7 @@ refclk: refclk { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <0x1312D00>; + clock-frequency = <0x17D7840>; clock-output-names = "xtal"; }; @@ -73,7 +73,7 @@ uart@10000000 { interrupts = <0x0a>; interrupt-parent = <0x03>; - clock-frequency = <0x1312D00>; + clock-frequency = <0x17D7840>; reg = <0x00 0x10000000 0x00 0x100>; compatible = "ns16550a"; }; diff --git a/linux/devicetree/wally-vcu108.dts b/linux/devicetree/wally-vcu108.dts index 8c9182c6c..01deddc6e 100644 --- a/linux/devicetree/wally-vcu108.dts +++ b/linux/devicetree/wally-vcu108.dts @@ -9,7 +9,7 @@ chosen { linux,initrd-end = <0x85c43a00>; linux,initrd-start = <0x84200000>; - bootargs = "console=ttyS0,115200 root=/dev/vda ro"; + bootargs = "root=/dev/vda ro console=ttyS0,115200 loglevel=7"; stdout-path = "/soc/uart@10000000"; }; @@ -21,8 +21,8 @@ cpus { #address-cells = <0x01>; #size-cells = <0x00>; - clock-frequency = <0x14FB180>; - timebase-frequency = <0x14FB180>; + clock-frequency = <0x2FAF080>; + timebase-frequency = <0x2FAF080>; cpu@0 { phandle = <0x01>; @@ -31,6 +31,9 @@ status = "okay"; compatible = "riscv"; riscv,isa = "rv64imafdcsu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zicbom", "zicbop", "zicbopz", "zicntr", "zicsr", "zifencei", "zihpm"; + riscv,cbom-block-size = <64>; mmu-type = "riscv,sv48"; interrupt-controller { @@ -48,10 +51,29 @@ compatible = "simple-bus"; ranges; + refclk: refclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0x2FAF080>; + clock-output-names = "xtal"; + }; + + gpio0: gpio@10060000 { + compatible = "sifive,gpio0"; + interrupt-parent = <0x03>; + interrupts = <3>; + reg = <0x00 0x10060000 0x00 0x1000>; + reg-names = "control"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + uart@10000000 { interrupts = <0x0a>; interrupt-parent = <0x03>; - clock-frequency = <0x14FB180>; + clock-frequency = <0x2FAF080>; reg = <0x00 0x10000000 0x00 0x100>; compatible = "ns16550a"; }; @@ -67,18 +89,24 @@ #address-cells = <0x00>; }; - mmc@13000 { - interrupts = <0x14>; - compatible = "riscv,axi-sd-card-1.0"; - reg = <0x00 0x13000 0x00 0x7F>; - fifo-depth = <256>; - bus-width = <4>; + spi@13000 { + compatible = "sifive,spi0"; interrupt-parent = <0x03>; - clock = <0x14FB180>; - max-frequency = <0xA7D8C0>; - cap-sd-highspeed; - cap-mmc-highspeed; - no-sdio; + interrupts = <0x14>; + reg = <0x0 0x13000 0x0 0x1000>; + reg-names = "control"; + clocks = <&refclk>; + + #address-cells = <1>; + #size-cells = <0>; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <1000000>; + voltage-ranges = <3300 3300>; + disable-wp; + // gpios = <&gpio0 6 1>; + }; }; clint@2000000 { diff --git a/linux/testvector-generation/parseGDBtoTrace.py b/linux/testvector-generation/parseGDBtoTrace.py index a5ace11b0..96ad464ed 100755 --- a/linux/testvector-generation/parseGDBtoTrace.py +++ b/linux/testvector-generation/parseGDBtoTrace.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 import sys, fileinput, re -# Ross Thompson +# Rose Thompson # July 27, 2021 # Rewrite of the linux trace parser. diff --git a/sim/Makefile b/sim/Makefile index fe413ce15..e88238fb2 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -30,8 +30,8 @@ QuestaCodeCoverage: questa/ucdb/rv64gc_arch64i.ucdb # vcover report -recursive questa/ucdb/cov.ucdb > questa/cov/rv64gc_recursive.rpt vcover report -details -threshH 100 -html questa/ucdb/cov.ucdb -QuestaFunctCoverage: ${SIM}/questa/fcov_ucdb/rv64gc_WALLY-COV-add.elf.ucdb - vcover merge -out ${SIM}/questa/fcov_ucdb/fcov.ucdb ${SIM}/questa/fcov_ucdb/rv64gc_WALLY-COV-add.elf.ucdb ${SIM}/questa/fcov_ucdb/rv64gc_WALLY*.ucdb -logfile ${SIM}/questa/fcov_logs/log +QuestaFunctCoverage: ${SIM}/questa/fcov_ucdb/rv64gc_I_WALLY-COV-add.elf.ucdb + vcover merge -out ${SIM}/questa/fcov_ucdb/fcov.ucdb ${SIM}/questa/fcov_ucdb/rv64gc_I_WALLY-COV-add.elf.ucdb ${SIM}/questa/fcov_ucdb/rv64gc_I_WALLY*.ucdb -logfile ${SIM}/questa/fcov_logs/log vcover report -details -html ${SIM}/questa/fcov_ucdb/fcov.ucdb vcover report ${SIM}/questa/fcov_ucdb/fcov.ucdb -details -cvg > ${SIM}/questa/fcov/fcov.log vcover report ${SIM}/questa/fcov_ucdb/fcov.ucdb -testdetails -cvg > ${SIM}/questa/fcov/fcov.testdetails.log diff --git a/sim/questa/wally.do b/sim/questa/wally.do index 52731819f..80a7bef76 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -233,7 +233,7 @@ set temp3 [lindex $PlusArgs 3] # "Extra checking for conflicts with always_comb done at vopt time" # because vsim will run vopt -vlog -lint -work ${WKDIR} +incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared ${lockstepvoptstring} ${FCdefineIDV_INCLUDE_TRACE2COV} ${FCdefineINCLUDE_TRACE2COV} ${ImperasPubInc} ${ImperasPrivInc} ${rvviFiles} ${FCdefineCOVER_BASE_RV64I} ${FCdefineCOVER_LEVEL_DV_PR_EXT} ${FCdefineCOVER_RV64I} ${FCdefineCOVER_RV64M} ${FCdefineCOVER_RV64A} ${FCdefineCOVER_RV64F} ${FCdefineCOVER_RV64D} ${FCdefineCOVER_RV64ZICSR} ${FCdefineCOVER_RV64C} ${FCdefineRVVI_COVERAGE} ${idvFiles} ${riscvISACOVsrc} ${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv +incdir+${FCRVVI}/common +incdir+${FCRVVI} ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 +vlog -lint +nowarnRDGN -suppress 2244 -work ${WKDIR} +incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared ${lockstepvoptstring} ${FCdefineIDV_INCLUDE_TRACE2COV} ${FCdefineINCLUDE_TRACE2COV} ${ImperasPubInc} ${ImperasPrivInc} ${rvviFiles} ${FCdefineCOVER_BASE_RV64I} ${FCdefineCOVER_LEVEL_DV_PR_EXT} ${FCdefineCOVER_RV64I} ${FCdefineCOVER_RV64M} ${FCdefineCOVER_RV64A} ${FCdefineCOVER_RV64F} ${FCdefineCOVER_RV64D} ${FCdefineCOVER_RV64ZICSR} ${FCdefineCOVER_RV64C} ${FCdefineRVVI_COVERAGE} ${idvFiles} ${riscvISACOVsrc} ${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv +incdir+${FCRVVI}/common +incdir+${FCRVVI} ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv -suppress 2244 -suppress 2282 -suppress 2583 -suppress 7063,2596,13286 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals diff --git a/sim/questa/wave.do b/sim/questa/wave.do index 201002d7d..572ae05db 100644 --- a/sim/questa/wave.do +++ b/sim/questa/wave.do @@ -204,228 +204,228 @@ add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcAE add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcBE add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ALUResultE add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ResultW -add wave -noupdate -expand -group {Memory Stage} /testbench/FunctionName/FunctionName -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrValidM -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM -add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/WriteDataM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/FWriteDataM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM -add wave -noupdate -expand -group lsu -group stalls /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall -add wave -noupdate -expand -group lsu -group stalls /testbench/dut/core/lsu/IgnoreRequestTLB -add wave -noupdate -expand -group lsu -group stalls /testbench/dut/core/lsu/SelHPTW -add wave -noupdate -expand -group lsu -group stalls /testbench/dut/core/lsu/LSUStallM -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK -add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr -add wave -noupdate -expand -group lsu -group alignment -color Gold /testbench/dut/core/lsu/ziccslm_align/align/CurrState -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/MemRWM -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/IEUAdrSpillM -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskM -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskExtendedM -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/SelSpillE -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/SelSpillM -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskSpillM -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataM -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataSpillM -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteData -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/ByteMask -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/BlankByteMask -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/DemuxedByteMask -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/FetchBufferByteSel -add wave -noupdate -expand -group lsu -group alignment {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/LineWriteData} -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IEUAdrExtE -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IEUAdrExtM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/NextSet -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOpM -add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group {requesting address} /testbench/dut/core/lsu/IEUAdrE -add wave -noupdate -expand -group lsu -expand -group dcache -group {requesting address} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLineWay -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLineCache -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/TagWay -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/Tag -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ValidWay -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs -color {Blue Violet} /testbench/dut/core/lsu/bus/dcache/dcache/Hit -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/DirtyWay -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitDirtyWay -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitLineDirty -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelWriteback -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/LineByteMask -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/bwe} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/bwe} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/bwe} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ce} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/bwe} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ClearValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ClearValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ClearValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/TagWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/TagWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/TagWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/TagWay} -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBHit -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr -add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal -add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk -add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextWalkerState -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE -add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM -add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF -add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM -add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWFaultM -add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM -add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF -add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM -add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM -add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault -add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/PBMTFaultM +add wave -noupdate -group {Memory Stage} /testbench/FunctionName/FunctionName/FunctionName +add wave -noupdate -group {Memory Stage} /testbench/dut/core/InstrValidM +add wave -noupdate -group {Memory Stage} /testbench/dut/core/PCM +add wave -noupdate -group {Memory Stage} /testbench/dut/core/InstrM +add wave -noupdate -group {Memory Stage} /testbench/InstrMName +add wave -noupdate -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM +add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM +add wave -noupdate -group lsu /testbench/dut/core/lsu/WriteDataM +add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM +add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM +add wave -noupdate -group lsu -group stalls /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall +add wave -noupdate -group lsu -group stalls /testbench/dut/core/lsu/IgnoreRequestTLB +add wave -noupdate -group lsu -group stalls /testbench/dut/core/lsu/SelHPTW +add wave -noupdate -group lsu -group stalls /testbench/dut/core/lsu/LSUStallM +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK +add wave -noupdate -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr +add wave -noupdate -group lsu -group alignment -color Gold /testbench/dut/core/lsu/ziccslm_align/align/CurrState +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/MemRWM +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/IEUAdrSpillM +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskM +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskExtendedM +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/SelSpillE +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/SelSpillM +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskSpillM +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataM +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataSpillM +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteData +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/ByteMask +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/BlankByteMask +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/DemuxedByteMask +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/FetchBufferByteSel +add wave -noupdate -group lsu -group alignment {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/LineWriteData} +add wave -noupdate -group lsu /testbench/dut/core/lsu/IEUAdrExtE +add wave -noupdate -group lsu /testbench/dut/core/lsu/IEUAdrExtM +add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/NextSet +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOpM +add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState +add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid +add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -group lsu -expand -group dcache -group {requesting address} /testbench/dut/core/lsu/IEUAdrE +add wave -noupdate -group lsu -expand -group dcache -group {requesting address} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLineWay +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLineCache +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/TagWay +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/Tag +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ValidWay +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs -color {Blue Violet} /testbench/dut/core/lsu/bus/dcache/dcache/Hit +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/DirtyWay +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitDirtyWay +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitLineDirty +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelWriteback +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/LineByteMask +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/bwe} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/bwe} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/bwe} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ce} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/bwe} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ClearValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ClearValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ClearValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/TagWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/TagWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/TagWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/TagWay} +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBHit +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress +add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault +add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM +add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr +add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal +add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM +add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW +add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall +add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk +add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState +add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextWalkerState +add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr +add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE +add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType +add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType +add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE +add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM +add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF +add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM +add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWFaultM +add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM +add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF +add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM +add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM +add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM +add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM +add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault +add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/PBMTFaultM add wave -noupdate -group {WriteBack stage} /testbench/InstrW add wave -noupdate -group {WriteBack stage} /testbench/InstrWName add wave -noupdate -group {WriteBack stage} /testbench/dut/core/priv/priv/pmd/wfiW @@ -468,88 +468,88 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK -add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HADDR -add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HTRANS -add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HREADY -add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HSELRegions -add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HSELNoneD -add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HSELPLICD -add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HRDATA -add wave -noupdate -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/UARTIntr -add wave -noupdate -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/GPIOIntr -add wave -noupdate -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/MExtInt -add wave -noupdate -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/SExtInt -add wave -noupdate -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/Dout -add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intClaim -add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intEn -add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intInProgress -add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intPending -add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intPriority -add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intThreshold -add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/nextIntPending -add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/requests -add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/irqMatrix -add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/priorities_with_irqs -add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/max_priority_with_irqs -add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/irqs_at_max_priority -add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/threshMask -add wave -noupdate -group uncore -group CLINT /testbench/dut/uncoregen/uncore/clint/clint/MTIME -add wave -noupdate -group uncore -group CLINT /testbench/dut/uncoregen/uncore/clint/clint/MTIMECMP -add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PSEL -add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PADDR -add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PWDATA -add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PSTRB -add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PWRITE -add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PENABLE -add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PRDATA -add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PREADY -add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/LSR -add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/MCR -add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/MSR -add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/RBR -add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/TXHR -add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/LCR -add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/intrID -add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/INTR -add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxstate -add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/txstate -add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/txbitssent -add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/txbitsexpected -add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxbitsreceived -add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxbitsexpected -add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxdata -add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxoverrunerr -add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxdataready -add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxdataavailintr -add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/RXBR -add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/squashRXerrIP -add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxshiftreg -add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/SOUTbit -add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/SINsync -add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/txsr -add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/SIN -add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/SOUT -add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/RTSb -add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/DTRb -add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/OUT1b -add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/OUT2b -add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/DSRb -add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/DCDb -add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/CTSb -add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/TXRDYb -add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/RXRDYb -add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/GPIOIN -add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/GPIOOUT -add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/GPIOEN -add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/GPIOIntr -add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PSEL -add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PADDR -add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PWRITE -add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PRDATA -add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PREADY -add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PWDATA -add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PSTRB -add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PENABLE +add wave -noupdate -expand -group uncore /testbench/dut/uncoregen/uncore/HADDR +add wave -noupdate -expand -group uncore /testbench/dut/uncoregen/uncore/HTRANS +add wave -noupdate -expand -group uncore /testbench/dut/uncoregen/uncore/HREADY +add wave -noupdate -expand -group uncore /testbench/dut/uncoregen/uncore/HSELRegions +add wave -noupdate -expand -group uncore /testbench/dut/uncoregen/uncore/HSELNoneD +add wave -noupdate -expand -group uncore /testbench/dut/uncoregen/uncore/HSELPLICD +add wave -noupdate -expand -group uncore /testbench/dut/uncoregen/uncore/HRDATA +add wave -noupdate -expand -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/UARTIntr +add wave -noupdate -expand -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/GPIOIntr +add wave -noupdate -expand -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/MExtInt +add wave -noupdate -expand -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/SExtInt +add wave -noupdate -expand -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/Dout +add wave -noupdate -expand -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intClaim +add wave -noupdate -expand -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intEn +add wave -noupdate -expand -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intInProgress +add wave -noupdate -expand -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intPending +add wave -noupdate -expand -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intPriority +add wave -noupdate -expand -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intThreshold +add wave -noupdate -expand -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/nextIntPending +add wave -noupdate -expand -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/requests +add wave -noupdate -expand -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/irqMatrix +add wave -noupdate -expand -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/priorities_with_irqs +add wave -noupdate -expand -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/max_priority_with_irqs +add wave -noupdate -expand -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/irqs_at_max_priority +add wave -noupdate -expand -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/threshMask +add wave -noupdate -expand -group uncore -group CLINT /testbench/dut/uncoregen/uncore/clint/clint/MTIME +add wave -noupdate -expand -group uncore -group CLINT /testbench/dut/uncoregen/uncore/clint/clint/MTIMECMP +add wave -noupdate -expand -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PSEL +add wave -noupdate -expand -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PADDR +add wave -noupdate -expand -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PWDATA +add wave -noupdate -expand -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PSTRB +add wave -noupdate -expand -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PWRITE +add wave -noupdate -expand -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PENABLE +add wave -noupdate -expand -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PRDATA +add wave -noupdate -expand -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PREADY +add wave -noupdate -expand -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/LSR +add wave -noupdate -expand -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/MCR +add wave -noupdate -expand -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/MSR +add wave -noupdate -expand -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/RBR +add wave -noupdate -expand -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/TXHR +add wave -noupdate -expand -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/LCR +add wave -noupdate -expand -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/intrID +add wave -noupdate -expand -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/INTR +add wave -noupdate -expand -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxstate +add wave -noupdate -expand -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/txstate +add wave -noupdate -expand -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/txbitssent +add wave -noupdate -expand -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/txbitsexpected +add wave -noupdate -expand -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxbitsreceived +add wave -noupdate -expand -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxbitsexpected +add wave -noupdate -expand -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxdata +add wave -noupdate -expand -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxoverrunerr +add wave -noupdate -expand -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxdataready +add wave -noupdate -expand -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxdataavailintr +add wave -noupdate -expand -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/RXBR +add wave -noupdate -expand -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/squashRXerrIP +add wave -noupdate -expand -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxshiftreg +add wave -noupdate -expand -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/SOUTbit +add wave -noupdate -expand -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/SINsync +add wave -noupdate -expand -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/txsr +add wave -noupdate -expand -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/SIN +add wave -noupdate -expand -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/SOUT +add wave -noupdate -expand -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/RTSb +add wave -noupdate -expand -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/DTRb +add wave -noupdate -expand -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/OUT1b +add wave -noupdate -expand -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/OUT2b +add wave -noupdate -expand -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/DSRb +add wave -noupdate -expand -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/DCDb +add wave -noupdate -expand -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/CTSb +add wave -noupdate -expand -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/TXRDYb +add wave -noupdate -expand -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/RXRDYb +add wave -noupdate -expand -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/GPIOIN +add wave -noupdate -expand -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/GPIOOUT +add wave -noupdate -expand -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/GPIOEN +add wave -noupdate -expand -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/GPIOIntr +add wave -noupdate -expand -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PSEL +add wave -noupdate -expand -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PADDR +add wave -noupdate -expand -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PWRITE +add wave -noupdate -expand -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PRDATA +add wave -noupdate -expand -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PREADY +add wave -noupdate -expand -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PWDATA +add wave -noupdate -expand -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PSTRB +add wave -noupdate -expand -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PENABLE add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rf add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1 add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2 @@ -657,25 +657,21 @@ add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/WFITimeoutM add wave -noupdate -expand -group testbench /testbench/DCacheFlushStart add wave -noupdate /testbench/dut/core/lsu/hptw/hptw/HPTWLoadPageFault add wave -noupdate /testbench/dut/core/lsu/hptw/hptw/HPTWLoadPageFaultDelay -add wave -noupdate -expand -group rvvi /testbench/rvvi_synth/rvvisynth/clk -add wave -noupdate -expand -group rvvi /testbench/rvvi_synth/rvvisynth/rvvi -add wave -noupdate -expand -group rvvi /testbench/rvvi_synth/rvvisynth/valid -add wave -noupdate -group packetizer -color Gold /testbench/rvvi_synth/packetizer/CurrState -add wave -noupdate -group packetizer -radix unsigned /testbench/rvvi_synth/packetizer/WordCount -add wave -noupdate -group packetizer /testbench/rvvi_synth/packetizer/RVVIStall -add wave -noupdate -group packetizer /testbench/rvvi_synth/packetizer/rvviDelay -add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/RvviAxiWdata -add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/RvviAxiWlast -add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/RvviAxiWstrb -add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/RvviAxiWvalid -add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/RvviAxiWready -add wave -noupdate -expand -group eth /testbench/rvvi_synth/ethernet/mii_tx_clk -add wave -noupdate -expand -group eth /testbench/rvvi_synth/ethernet/mii_txd -add wave -noupdate -expand -group eth /testbench/rvvi_synth/ethernet/mii_tx_en -add wave -noupdate -expand -group eth /testbench/rvvi_synth/ethernet/mii_tx_er +add wave -noupdate -expand -group spi /testbench/dut/uncoregen/uncore/spi/spi/PCLK +add wave -noupdate -expand -group spi -expand -group interface /testbench/dut/uncoregen/uncore/spi/spi/SPICLK +add wave -noupdate -expand -group spi -expand -group interface /testbench/dut/uncoregen/uncore/spi/spi/SPICS +add wave -noupdate -expand -group spi -expand -group interface /testbench/dut/uncoregen/uncore/spi/spi/SPIOut +add wave -noupdate -expand -group spi -expand -group interface /testbench/dut/uncoregen/uncore/spi/spi/SPIIn +add wave -noupdate -expand -group spi /testbench/dut/uncoregen/uncore/spi/spi/ChipSelectMode +add wave -noupdate -expand -group spi /testbench/dut/uncoregen/uncore/spi/spi/SckMode +add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/TransmitShiftRegLoad +add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/ShiftEdge +add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/Active +add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/TransmitData +add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/TransmitShiftReg TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {640 ns} 1} {{Cursor 4} {2400 ns} 1} {{Cursor 3} {554 ns} 0} {{Cursor 4} {120089 ns} 0} -quietly wave cursor active 4 +WaveRestoreCursors {{Cursor 4} {640 ns} 1} {{Cursor 4} {2400 ns} 1} {{Cursor 3} {214070 ns} 0} {{Cursor 4} {223860 ns} 1} +quietly wave cursor active 3 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 configure wave -justifyvalue left @@ -690,4 +686,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {0 ns} {1033211 ns} +WaveRestoreZoom {213740 ns} {214380 ns} diff --git a/src/cache/cache.sv b/src/cache/cache.sv index 44966f03c..4c89d08cc 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // cache.sv // -// Written: Ross Thompson ross1728@gmail.com +// Written: Rose Thompson ross1728@gmail.com // Created: 7 July 2021 // Modified: 20 January 2023 // diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 64084f863..28cdc7440 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // cachefsm.sv // -// Written: Ross Thompson ross1728@gmail.com +// Written: Rose Thompson ross1728@gmail.com // Created: 25 August 2021 // Modified: 20 January 2023 // diff --git a/src/cache/subcachelineread.sv b/src/cache/subcachelineread.sv index 3e9718c27..2c340c092 100644 --- a/src/cache/subcachelineread.sv +++ b/src/cache/subcachelineread.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // subcachelineread.sv // -// Written: Ross Thompson ross1728@gmail.com +// Written: Rose Thompson ross1728@gmail.com // Created: 4 February 2022 // Modified: 20 January 2023 // diff --git a/src/ebu/ahbcacheinterface.sv b/src/ebu/ahbcacheinterface.sv index 2e6973ba5..572e824bb 100644 --- a/src/ebu/ahbcacheinterface.sv +++ b/src/ebu/ahbcacheinterface.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ahbcacheinterface.sv // -// Written: Ross Thompson ross1728@gmail.com +// Written: Rose Thompson ross1728@gmail.com // Created: August 29, 2022 // Modified: 18 January 2023 // diff --git a/src/ebu/ahbinterface.sv b/src/ebu/ahbinterface.sv index a9bf8f497..821633f71 100644 --- a/src/ebu/ahbinterface.sv +++ b/src/ebu/ahbinterface.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ahbinterface.sv // -// Written: Ross Thompson ross1728@gmail.com +// Written: Rose Thompson ross1728@gmail.com // Created: August 29, 2022 // Modified: 18 January 2023 // diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv index 623d17975..9461bd5c5 100644 --- a/src/ebu/buscachefsm.sv +++ b/src/ebu/buscachefsm.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // busfsm.sv // -// Written: Ross Thompson ross1728@gmail.com +// Written: Rose Thompson ross1728@gmail.com // Created: December 29, 2021 // Modified: 18 January 2023 // diff --git a/src/ebu/busfsm.sv b/src/ebu/busfsm.sv index 8aa640673..9080dbb83 100644 --- a/src/ebu/busfsm.sv +++ b/src/ebu/busfsm.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // busfsm.sv // -// Written: Ross Thompson ross1728@gmail.com +// Written: Rose Thompson ross1728@gmail.com // Created: December 29, 2021 // Modified: 18 January 2023 // diff --git a/src/ebu/controllerinput.sv b/src/ebu/controllerinput.sv index 97ea0d5b4..1c4c360ec 100644 --- a/src/ebu/controllerinput.sv +++ b/src/ebu/controllerinput.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // controllerinput.sv // -// Written: Ross Thompson ross1728@gmail.com +// Written: Rose Thompson ross1728@gmail.com // Created: August 31, 2022 // Modified: 18 January 2023 // diff --git a/src/ebu/ebu.sv b/src/ebu/ebu.sv index edf1461bb..8242d27e6 100644 --- a/src/ebu/ebu.sv +++ b/src/ebu/ebu.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // abhmulticontroller // -// Written: Ross Thompson ross1728@gmail.com +// Written: Rose Thompson ross1728@gmail.com // Created: August 29, 2022 // Modified: 18 January 2023 // diff --git a/src/ebu/ebufsmarb.sv b/src/ebu/ebufsmarb.sv index daf3da1e8..2e7b345f2 100644 --- a/src/ebu/ebufsmarb.sv +++ b/src/ebu/ebufsmarb.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ebufsmarb.sv // -// Written: Ross Thompson ross1728@gmail.com +// Written: Rose Thompson ross1728@gmail.com // Created: 23 January 2023 // Modified: 23 January 2023 // diff --git a/src/generic/arrs.sv b/src/generic/arrs.sv index cbff0e82b..c0d314dd5 100644 --- a/src/generic/arrs.sv +++ b/src/generic/arrs.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // arrs.sv // -// Written: Ross Thompson ross1728@gmail.com +// Written: Rose Thompson ross1728@gmail.com // Modified: November 12, 2021 // // Purpose: resets are typically asynchronous but need to be synchronized to diff --git a/src/ifu/bpred/RASPredictor.sv b/src/ifu/bpred/RASPredictor.sv index b3f13d010..d72f0e0d8 100644 --- a/src/ifu/bpred/RASPredictor.sv +++ b/src/ifu/bpred/RASPredictor.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // RASPredictor.sv // -// Written: Ross Thomposn ross1728@gmail.com +// Written: Rose Thomposn ross1728@gmail.com // Created: 15 February 2021 // Modified: 25 January 2023 // diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index da8a7a2a2..8d6a55d75 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // bpred.sv // -// Written: Ross Thomposn ross1728@gmail.com +// Written: Rose Thomposn ross1728@gmail.com // Created: 12 February 2021 // Modified: 19 January 2023 // diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv index acd61df67..e0ee0aaf4 100644 --- a/src/ifu/bpred/btb.sv +++ b/src/ifu/bpred/btb.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // btb.sv // -// Written: Ross Thompson ross1728@gmail.com +// Written: Rose Thompson ross1728@gmail.com // Created: February 15, 2021 // Modified: 24 January 2023 // diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv index 691926484..057993536 100644 --- a/src/ifu/bpred/gshare.sv +++ b/src/ifu/bpred/gshare.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // gshare.sv // -// Written: Ross Thompson +// Written: Rose Thompson // Email: ross1728@gmail.com // Created: 16 March 2021 // Adapted from ssanghai@hmc.edu (Shreya Sanghai) diff --git a/src/ifu/bpred/gsharebasic.sv b/src/ifu/bpred/gsharebasic.sv index 61c3f55f0..a0563d809 100644 --- a/src/ifu/bpred/gsharebasic.sv +++ b/src/ifu/bpred/gsharebasic.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // gsharebasic.sv // -// Written: Ross Thompson +// Written: Rose Thompson // Email: ross1728@gmail.com // Created: 16 March 2021 // Adapted from ssanghai@hmc.edu (Shreya Sanghai) global history predictor implementation. diff --git a/src/ifu/bpred/icpred.sv b/src/ifu/bpred/icpred.sv index f8eec8742..01ebaca01 100644 --- a/src/ifu/bpred/icpred.sv +++ b/src/ifu/bpred/icpred.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // icpred.sv // -// Written: Ross Thomposn ross1728@gmail.com +// Written: Rose Thomposn ross1728@gmail.com // Created: February 26, 2023 // Modified: February 26, 2023 // diff --git a/src/ifu/bpred/localaheadbp.sv b/src/ifu/bpred/localaheadbp.sv index 5d290e85e..a2c7bda5a 100644 --- a/src/ifu/bpred/localaheadbp.sv +++ b/src/ifu/bpred/localaheadbp.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // localaheadbp // -// Written: Ross Thompson +// Written: Rose Thompson // Email: ross1728@gmail.com // Created: 16 March 2021 // diff --git a/src/ifu/bpred/localbpbasic.sv b/src/ifu/bpred/localbpbasic.sv index c2f3fdff3..b5634ef8a 100644 --- a/src/ifu/bpred/localbpbasic.sv +++ b/src/ifu/bpred/localbpbasic.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // localbpbasic // -// Written: Ross Thompson +// Written: Rose Thompson // Email: ross1728@gmail.com // Created: 16 March 2021 // diff --git a/src/ifu/bpred/localrepairbp.sv b/src/ifu/bpred/localrepairbp.sv index 7294816a1..5bb614d7f 100644 --- a/src/ifu/bpred/localrepairbp.sv +++ b/src/ifu/bpred/localrepairbp.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // localrepairbp // -// Written: Ross Thompson +// Written: Rose Thompson // Email: ross1728@gmail.com // Created: 15 April 2023 // diff --git a/src/ifu/bpred/satCounter2.sv b/src/ifu/bpred/satCounter2.sv index 7dd33ffb3..f59cef82b 100644 --- a/src/ifu/bpred/satCounter2.sv +++ b/src/ifu/bpred/satCounter2.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // satCounter2.sv // -// Written: Ross Thomposn +// Written: Rose Thomposn // Email: ross1728@gmail.com // Created: February 13, 2021 // Modified: diff --git a/src/ifu/bpred/twoBitPredictor.sv b/src/ifu/bpred/twoBitPredictor.sv index b65fdde7e..52a04d6e4 100644 --- a/src/ifu/bpred/twoBitPredictor.sv +++ b/src/ifu/bpred/twoBitPredictor.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // twoBitPredictor.sv // -// Written: Ross Thomposn +// Written: Rose Thomposn // Email: ross1728@gmail.com // Created: February 14, 2021 // Modified: diff --git a/src/ifu/irom.sv b/src/ifu/irom.sv index 027c26235..ebebfbe4a 100644 --- a/src/ifu/irom.sv +++ b/src/ifu/irom.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // irom.sv // -// Written: Ross Thompson ross1728@gmail.com +// Written: Rose Thompson ross1728@gmail.com // Created: 30 January 2022 // Modified: 18 January 2023 // diff --git a/src/ifu/spill.sv b/src/ifu/spill.sv index b2ee6e9e2..c3c518913 100644 --- a/src/ifu/spill.sv +++ b/src/ifu/spill.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // spill.sv // -// Written: Ross Thompson ross1728@gmail.com +// Written: Rose Thompson ross1728@gmail.com // Created: 28 January 2022 // Modified: 19 January 2023 // diff --git a/src/lsu/atomic.sv b/src/lsu/atomic.sv index 1e3419dec..9c37b636c 100644 --- a/src/lsu/atomic.sv +++ b/src/lsu/atomic.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // atomic.sv // -// Written: Ross Thompson ross1728@gmail.com +// Written: Rose Thompson ross1728@gmail.com // Created: 31 January 2022 // Modified: 18 January 2023 // diff --git a/src/lsu/dtim.sv b/src/lsu/dtim.sv index f46bcbd20..3fb6c81f6 100644 --- a/src/lsu/dtim.sv +++ b/src/lsu/dtim.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // dtim.sv // -// Written: Ross Thompson ross1728@gmail.com +// Written: Rose Thompson ross1728@gmail.com // Created: 30 January 2022 // Modified: 18 January 2023 // diff --git a/src/uncore/spi_apb.sv b/src/uncore/spi_apb.sv index 9bcf8be05..0701956a3 100644 --- a/src/uncore/spi_apb.sv +++ b/src/uncore/spi_apb.sv @@ -148,7 +148,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( // APB access assign Entry = {PADDR[7:2],2'b00}; // 32-bit word-aligned accesses assign Memwrite = PWRITE & PENABLE & PSEL; // Only write in access phase - assign PREADY = Entry == SPI_TXDATA | Entry == SPI_RXDATA | TransmitInactive; // Tie PREADY to transmission for hardware interlock + assign PREADY = Entry == SPI_TXDATA | Entry == SPI_RXDATA | Entry == SPI_IP | TransmitInactive; // Tie PREADY to transmission for hardware interlock // Account for subword read/write circuitry // -- Note SPI registers are 32 bits no matter what; access them with LW SW. diff --git a/testbench/common/DCacheFlushFSM.sv b/testbench/common/DCacheFlushFSM.sv index 752c8322d..cde584af2 100644 --- a/testbench/common/DCacheFlushFSM.sv +++ b/testbench/common/DCacheFlushFSM.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // DCacheFlushFSM.sv // -// Written: David Harris David_Harris@hmc.edu and Ross Thompson ross1728@gmail.com +// Written: David Harris David_Harris@hmc.edu and Rose Thompson ross1728@gmail.com // Modified: 14 June 2023 // // Purpose: The L1 data cache and any feature L2 or high cache will not necessary writeback all dirty diff --git a/testbench/common/functionName.sv b/testbench/common/functionName.sv index c08b1d767..eac58f40a 100644 --- a/testbench/common/functionName.sv +++ b/testbench/common/functionName.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // functionName.sv // -// Written: Ross Thompson ross1728@gmail.com +// Written: Rose Thompson ross1728@gmail.com // // Purpose: decode name of function // diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv index 967cf672b..a9edb7892 100644 --- a/testbench/common/loggers.sv +++ b/testbench/common/loggers.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // loggers.sv // -// Written: Ross Thompson ross1728@gmail.com +// Written: Rose Thompson ross1728@gmail.com // Modified: 14 June 2023 // // Purpose: Log branch instructions, log instruction fetches, @@ -246,8 +246,8 @@ module loggers import cvw::*; #(parameter cvw_t P, flop #(1) ResetDReg(clk, reset, resetD); assign resetEdge = ~reset & resetD; initial begin - LogFile = "branch.log"; // will break some of Ross's research analysis scripts - CFILogFile = "cfi.log"; // will break some of Ross's research analysis scripts + LogFile = "branch.log"; // will break some of Rose's research analysis scripts + CFILogFile = "cfi.log"; // will break some of Rose's research analysis scripts //LogFile = $psprintf("branch_%s%0d.log", P.BPRED_TYPE, P.BPRED_SIZE); file = $fopen(LogFile, "w"); CFIfile = $fopen(CFILogFile, "w"); diff --git a/testbench/common/watchdog.sv b/testbench/common/watchdog.sv index 69b185c40..9dbf6fa8b 100644 --- a/testbench/common/watchdog.sv +++ b/testbench/common/watchdog.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // watchdog.sv // -// Written: Ross Thompson ross1728@gmail.com +// Written: Rose Thompson ross1728@gmail.com // Modified: 14 June 2023 // // Purpose: Detects if the processor is stuck and halts the simulation diff --git a/testbench/sdc/sdModel.sv b/testbench/sdc/sdModel.sv index 11f3ba5d7..34b88a18d 100644 --- a/testbench/sdc/sdModel.sv +++ b/testbench/sdc/sdModel.sv @@ -917,7 +917,7 @@ module sdModel WRITE_DATA: begin oeDat<=1; outdly_cnt<=outdly_cnt+1; - datOut <= 4'b1111; // listen... until I tell you otherwise, DAT bus is all high (thanks Ross) + datOut <= 4'b1111; // listen... until I tell you otherwise, DAT bus is all high (thanks Rose) if ( outdly_cnt > `DLY_TO_OUTP) begin // if (outdly_cnt > 47) NAC cycles elapsed diff --git a/tests/custom/fpga-test-sdc/copyFlash.c b/tests/custom/fpga-test-sdc/copyFlash.c index 4165fe21c..b78653779 100644 --- a/tests/custom/fpga-test-sdc/copyFlash.c +++ b/tests/custom/fpga-test-sdc/copyFlash.c @@ -1,7 +1,7 @@ /////////////////////////////////////////// // copyFlash.sv // -// Written: Ross Thompson September 25, 2021 +// Written: Rose Thompson September 25, 2021 // Modified: // // Purpose: copies flash card into memory diff --git a/tests/custom/fpga-test-sdc/sdcDriver.c b/tests/custom/fpga-test-sdc/sdcDriver.c index edbe0677d..45caa42fa 100644 --- a/tests/custom/fpga-test-sdc/sdcDriver.c +++ b/tests/custom/fpga-test-sdc/sdcDriver.c @@ -1,7 +1,7 @@ /////////////////////////////////////////// // SDC.sv // -// Written: Ross Thompson September 25, 2021 +// Written: Rose Thompson September 25, 2021 // Modified: // // Purpose: driver for sdc reader. diff --git a/tests/custom/simple/fail.s b/tests/custom/simple/fail.s index 552604fe2..84a049dbd 100644 --- a/tests/custom/simple/fail.s +++ b/tests/custom/simple/fail.s @@ -1,4 +1,4 @@ -# Ross Thompson +# Rose Thompson # March 17, 2021 # Oklahoma State University diff --git a/tests/custom/spitest/Makefile b/tests/custom/spitest/Makefile new file mode 100644 index 000000000..34e83a9e4 --- /dev/null +++ b/tests/custom/spitest/Makefile @@ -0,0 +1,112 @@ +CEXT := c +CPPEXT := cpp +AEXT := s +SEXT := S +SRCEXT := \([$(CEXT)$(AEXT)$(SEXT)]\|$(CPPEXT)\) +OBJEXT := o +DEPEXT := d +SRCDIR := . +BUILDDIR := OBJ + +SOURCES ?= $(shell find $(SRCDIR) -type f -regex ".*\.$(SRCEXT)" | sort) +OBJECTS := $(SOURCES:.$(CEXT)=.$(OBJEXT)) +OBJECTS := $(OBJECTS:.$(AEXT)=.$(OBJEXT)) +OBJECTS := $(OBJECTS:.$(SEXT)=.$(OBJEXT)) +OBJECTS := $(OBJECTS:.$(CPPEXT)=.$(OBJEXT)) +OBJECTS := $(patsubst $(SRCDIR)/%,$(BUILDDIR)/%,$(OBJECTS)) + +TARGETDIR := bin +TARGET := $(TARGETDIR)/spitest.elf +ROOT := .. +LIBRARY_DIRS := +LIBRARY_FILES := + +MARCH :=-march=rv64imfdc +MABI :=-mabi=lp64d +LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles +LINKER :=$(ROOT)/linker8000-0000.x + + +AFLAGS =$(MARCH) $(MABI) -W +CFLAGS =$(MARCH) $(MABI) -mcmodel=medany -O2 +AS=riscv64-unknown-elf-as +CC=riscv64-unknown-elf-gcc +AR=riscv64-unknown-elf-ar + + +#Default Make +all: directories $(TARGET).memfile + +#Remake +remake: clean all + +#Make the Directories +directories: + @mkdir -p $(TARGETDIR) + @mkdir -p $(BUILDDIR) + +clean: + rm -rf $(BUILDDIR) $(TARGETDIR) *.memfile *.objdump + + +#Needed for building additional library projects +ifdef LIBRARY_DIRS +LIBS+=${LIBRARY_DIRS:%=-L%} ${LIBRARY_FILES:%=-l%} +INC+=${LIBRARY_DIRS:%=-I%} + +${LIBRARY_DIRS}: + make -C $@ -j 1 + +.PHONY: $(LIBRARY_DIRS) $(TARGET) +endif + + +#Pull in dependency info for *existing* .o files +-include $(OBJECTS:.$(OBJEXT)=.$(DEPEXT)) + +#Link +$(TARGET): $(OBJECTS) $(LIBRARY_DIRS) + $(CC) $(LINK_FLAGS) -g -o $(TARGET) $(OBJECTS) ${LIBS} -T ${LINKER} + + +#Compile +$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(CEXT) + @mkdir -p $(dir $@) + $(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list + @$(CC) $(CFLAGS) $(INC) -MM $(SRCDIR)/$*.$(CEXT) > $(BUILDDIR)/$*.$(DEPEXT) + @cp -f $(BUILDDIR)/$*.$(DEPEXT) $(BUILDDIR)/$*.$(DEPEXT).tmp + @sed -e 's|.*:|$(BUILDDIR)/$*.$(OBJEXT):|' < $(BUILDDIR)/$*.$(DEPEXT).tmp > $(BUILDDIR)/$*.$(DEPEXT) + @sed -e 's/.*://' -e 's/\\$$//' < $(BUILDDIR)/$*.$(DEPEXT).tmp | fmt -1 | sed -e 's/^ *//' -e 's/$$/:/' >> $(BUILDDIR)/$*.$(DEPEXT) + @rm -f $(BUILDDIR)/$*.$(DEPEXT).tmp + +# gcc won't output dependencies for assembly files for some reason +# most asm files don't have dependencies so the echo will work for now. +$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(AEXT) + @mkdir -p $(dir $@) + $(CC) $(CFLAGS) -c -o $@ $< > $(BUILDDIR)/$*.list + @echo $@: $< > $(BUILDDIR)/$*.$(DEPEXT) + +$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(SEXT) + @mkdir -p $(dir $@) + $(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list + @echo $@: $< > $(BUILDDIR)/$*.$(DEPEXT) + +# C++ +$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(CPPEXT) + @mkdir -p $(dir $@) + $(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list + @$(CC) $(CFLAGS) $(INC) -MM $(SRCDIR)/$*.$(CPPEXT) > $(BUILDDIR)/$*.$(DEPEXT) + @cp -f $(BUILDDIR)/$*.$(DEPEXT) $(BUILDDIR)/$*.$(DEPEXT).tmp + @sed -e 's|.*:|$(BUILDDIR)/$*.$(OBJEXT):|' < $(BUILDDIR)/$*.$(DEPEXT).tmp > $(BUILDDIR)/$*.$(DEPEXT) + @sed -e 's/.*://' -e 's/\\$$//' < $(BUILDDIR)/$*.$(DEPEXT).tmp | fmt -1 | sed -e 's/^ *//' -e 's/$$/:/' >> $(BUILDDIR)/$*.$(DEPEXT) + @rm -f $(BUILDDIR)/$*.$(DEPEXT).tmp + +# convert to hex +$(TARGET).memfile: $(TARGET) + @echo 'Making object dump file.' + @riscv64-unknown-elf-objdump -D $< > $<.objdump + @echo 'Making memory file' + riscv64-unknown-elf-elf2hex --bit-width 64 --input $^ --output $@ + extractFunctionRadix.sh $<.objdump + mkdir -p ../work/ + cp -f $(TARGETDIR)/* ../work/ diff --git a/tests/custom/spitest/spi.h b/tests/custom/spitest/spi.h new file mode 100644 index 000000000..2b1d541da --- /dev/null +++ b/tests/custom/spitest/spi.h @@ -0,0 +1,116 @@ +/////////////////////////////////////////////////////////////////////// +// spi.h +// +// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024 +// +// Purpose: Header file for interfaceing with the SPI peripheral +// +// +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the +// “License”); you may not use this file except in compliance with the +// License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an “AS IS” BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +// implied. See the License for the specific language governing +// permissions and limitations under the License. +/////////////////////////////////////////////////////////////////////// + +#pragma once +#ifndef SPI_HEADER +#define SPI_HEADER + +#include + +#define SPI_BASE 0x13000 /* Base address of SPI device used for SDC */ + +/* register offsets */ +#define SPI_SCKDIV SPI_BASE + 0x00 /* Serial clock divisor */ +#define SPI_SCKMODE SPI_BASE + 0x04 /* Serial clock mode */ +#define SPI_CSID SPI_BASE + 0x10 /* Chip select ID */ +#define SPI_CSDEF SPI_BASE + 0x14 /* Chip select default */ +#define SPI_CSMODE SPI_BASE + 0x18 /* Chip select mode */ +#define SPI_DELAY0 SPI_BASE + 0x28 /* Delay control 0 */ +#define SPI_DELAY1 SPI_BASE + 0x2c /* Delay control 1 */ +#define SPI_FMT SPI_BASE + 0x40 /* Frame format */ +#define SPI_TXDATA SPI_BASE + 0x48 /* Tx FIFO data */ +#define SPI_RXDATA SPI_BASE + 0x4c /* Rx FIFO data */ +#define SPI_TXMARK SPI_BASE + 0x50 /* Tx FIFO [<35;39;29Mwatermark */ +#define SPI_RXMARK SPI_BASE + 0x54 /* Rx FIFO watermark */ + +/* Non-implemented +#define SPI_FCTRL SPI_BASE + 0x60 // SPI flash interface control +#define SPI_FFMT SPI_BASE + 0x64 // SPI flash instruction format +*/ +#define SPI_IE SPI_BASE + 0x70 /* Interrupt Enable Register */ +#define SPI_IP SPI_BASE + 0x74 /* Interrupt Pendings Register */ + +/* delay0 bits */ +#define SIFIVE_SPI_DELAY0_CSSCK(x) ((uint32_t)(x)) +#define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU +#define SIFIVE_SPI_DELAY0_SCKCS(x) ((uint32_t)(x) << 16) +#define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16) + +/* delay1 bits */ +#define SIFIVE_SPI_DELAY1_INTERCS(x) ((uint32_t)(x)) +#define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU +#define SIFIVE_SPI_DELAY1_INTERXFR(x) ((uint32_t)(x) << 16) +#define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16) + +/* csmode bits */ +#define SIFIVE_SPI_CSMODE_MODE_AUTO 0U +#define SIFIVE_SPI_CSMODE_MODE_HOLD 2U +#define SIFIVE_SPI_CSMODE_MODE_OFF 3U + +// inline void write_reg(uintptr_t addr, uint32_t value); +//inline uint32_t read_reg(uintptr_t addr); +//inline void spi_sendbyte(uint8_t byte); +//inline void waittx(); +//inline void waitrx(); +uint8_t spi_txrx(uint8_t byte); +uint8_t spi_dummy(); +//inline uint8_t spi_readbyte(); +//uint64_t spi_read64(); +void spi_init(); +void spi_set_clock(uint32_t clkin, uint32_t clkout); + +static inline void write_reg(uintptr_t addr, uint32_t value) { + volatile uint32_t * loc = (volatile uint32_t *) addr; + *loc = value; +} + +// Read a register +static inline uint32_t read_reg(uintptr_t addr) { + return *(volatile uint32_t *) addr; +} + +// Queues a single byte in the transfer fifo +static inline void spi_sendbyte(uint8_t byte) { + // Write byte to transfer fifo + write_reg(SPI_TXDATA, byte); +} + +static inline void waittx() { + while(!(read_reg(SPI_IP) & 1)) {} +} + +static inline void waitrx() { + while(read_reg(SPI_IP) & 2) {} +} + +static inline uint8_t spi_readbyte() { + return read_reg(SPI_RXDATA); +} + +#endif diff --git a/tests/custom/spitest/spitest.c b/tests/custom/spitest/spitest.c new file mode 100644 index 000000000..23d408c16 --- /dev/null +++ b/tests/custom/spitest/spitest.c @@ -0,0 +1,107 @@ +/////////////////////////////////////////////////////////////////////// +// spi.c +// +// Written: Jaocb Pease jacob.pease@okstate.edu 8/27/2024 +// +// Purpose: C code to test SPI bugs +// +// +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the +// “License”); you may not use this file except in compliance with the +// License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an “AS IS” BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +// implied. See the License for the specific language governing +// permissions and limitations under the License. +/////////////////////////////////////////////////////////////////////// + +#include "spi.h" + +// Testing SPI peripheral in loopback mode +// TODO: Need to make sure the configuration I'm using uses loopback +// mode. This can be specified in derivlists.txt +// TODO: + +uint8_t spi_txrx(uint8_t byte) { + spi_sendbyte(byte); + waittx(); + return spi_readbyte(); +} + +uint8_t spi_dummy() { + return spi_txrx(0xff); +} + +void spi_set_clock(uint32_t clkin, uint32_t clkout) { + uint32_t div = (clkin/(2*clkout)) - 1; + write_reg(SPI_SCKDIV, div); +} + +// Initialize Sifive FU540 based SPI Controller +void spi_init(uint32_t clkin) { + // Enable interrupts + write_reg(SPI_IE, 0x3); + + // Set TXMARK to 1. If the number of entries is < 1 + // IP's txwm field will go high. + // Set RXMARK to 0. If the number of entries is > 0 + // IP's rwxm field will go high. + write_reg(SPI_TXMARK, 1); + write_reg(SPI_RXMARK, 0); + + // Set Delay 0 to default + write_reg(SPI_DELAY0, + SIFIVE_SPI_DELAY0_CSSCK(1) | + SIFIVE_SPI_DELAY0_SCKCS(1)); + + // Set Delay 1 to default + write_reg(SPI_DELAY1, + SIFIVE_SPI_DELAY1_INTERCS(1) | + SIFIVE_SPI_DELAY1_INTERXFR(0)); + + // Initialize the SPI controller clock to + // div = (20MHz/(2*400kHz)) - 1 = 24 = 0x18 + write_reg(SPI_SCKDIV, 0x18); +} + +void main() { + spi_init(100000000); + + spi_set_clock(100000000,50000000); + + volatile uint8_t *p = (uint8_t *)(0x8F000000); + int j; + uint64_t n = 0; + + write_reg(SPI_CSMODE, SIFIVE_SPI_CSMODE_MODE_HOLD); + //n = 512/8; + + n = 4; + do { + // Send 8 dummy bytes (fifo should be empty) + for (j = 0; j < 8; j++) { + spi_sendbyte(0xaa + j); + } + + // Reset counter. Process bytes AS THEY COME IN. + for (j = 0; j < 8; j++) { + while (!(read_reg(SPI_IP) & 2)) {} + uint8_t x = spi_readbyte(); + *p++ = x; + } + } while(--n > 0); + + write_reg(SPI_CSMODE, SIFIVE_SPI_CSMODE_MODE_AUTO); +} diff --git a/tests/custom/spitest/start.s b/tests/custom/spitest/start.s new file mode 100644 index 000000000..57f66ce79 --- /dev/null +++ b/tests/custom/spitest/start.s @@ -0,0 +1,59 @@ +.section .init +.global _start +.type _start, @function + +_start: + # Initialize global pointer + .option push + .option norelax + 1:auipc gp, %pcrel_hi(__global_pointer$) + addi gp, gp, %pcrel_lo(1b) + .option pop + + li x1, 0 + li x2, 0 + li x4, 0 + li x5, 0 + li x6, 0 + li x7, 0 + li x8, 0 + li x9, 0 + li x10, 0 + li x11, 0 + li x12, 0 + li x13, 0 + li x14, 0 + li x15, 0 + li x16, 0 + li x17, 0 + li x18, 0 + li x19, 0 + li x20, 0 + li x21, 0 + li x22, 0 + li x23, 0 + li x24, 0 + li x25, 0 + li x26, 0 + li x27, 0 + li x28, 0 + li x29, 0 + li x30, 0 + li x31, 0 + + + + # set the stack pointer to the top of memory - 8 bytes (pointer size) + li sp, 0x87FFFFF8 + + jal ra, main + jal ra, _halt + +.section .text +.global _halt +.type _halt, @function +_halt: + li gp, 1 + li a0, 0 + ecall + j _halt