Fixed part of issue #405.

The non-cache version of the bus controller did not have the correct supression of BusCommitted for a read only controller.

src/ebu/ahbinterface.sv

@@ -64,7 +64,7 @@ module ahbinterface #(
     assign HWSTRB = '0;
   end    
 
-  busfsm busfsm(.HCLK, .HRESETn, .Flush, .BusRW,
+  busfsm #(~LSU) busfsm(.HCLK, .HRESETn, .Flush, .BusRW,
     .BusCommitted, .Stall, .BusStall, .CaptureEn, .HREADY,
     .HTRANS, .HWRITE);
 

src/ebu/busfsm.sv

@@ -28,7 +28,9 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 // HCLK and clk must be the same clock!
-module busfsm (
+module busfsm #(
+  parameter READ_ONLY
+)(
   input  logic       HCLK,
   input  logic       HRESETn,
 
@@ -70,7 +72,7 @@ module busfsm (
 //                  (CurrState == DATA_PHASE & ~BusRW[0]); // possible optimization here.  fails uart test, but i'm not sure the failure is valid.
                     (CurrState == DATA_PHASE); 
   
-  assign BusCommitted = CurrState != ADR_PHASE;
+  assign BusCommitted = CurrState != ADR_PHASE & ~(READ_ONLY & CurrState == MEM3);
 
   assign HTRANS = (CurrState == ADR_PHASE & HREADY & |BusRW & ~Flush) ? AHB_NONSEQ : AHB_IDLE;
   assign HWRITE = BusRW[0];