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added a delay to sel signals

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bbracker 2021-03-05 15:07:34 -05:00
parent a1223ee13b
commit 612f7a9ee4
1 changed files with 10 additions and 12 deletions
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22
wally-pipelined/src/uncore/uncore.sv
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@ -140,17 +140,15 @@ module uncore (
HSELUARTD); HSELUARTD);
// Synchronized Address Decoder (figure 4-2 in spec) // Address Decoder Delay (figure 4-2 in spec)
always_ff @(posedge HCLK) begin flopr #(1) hseltimreg(HCLK, ~HRESETn, HSELTim, HSELTimD);
HSELTimD <= HSELTim; flopr #(1) hselclintreg(HCLK, ~HRESETn, HSELCLINT, HSELCLINTD);
HSELCLINTD <= HSELCLINT; `ifdef GPIOBASE
`ifdef GPIOBASE flopr #(1) hselgpioreg(HCLK, ~HRESETn, HSELGPIO, HSELGPIOD);
HSELGPIOD <= HSELGPIO; `endif
`endif flopr #(1) hseluartreg(HCLK, ~HRESETn, HSELUART, HSELUARTD);
HSELUARTD <= HSELUART; `ifdef BOOTTIMBASE
`ifdef BOOTTIMBASE flopr #(1) hselboottimreg(HCLK, ~HRESETn, HSELBootTim, HSELBootTimD);
HSELBootTimD <= HSELBootTim; `endif
`endif
end
endmodule endmodule