Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

examples/verilog/fulladder/fulladder.sv

@@ -0,0 +1,52 @@
+module testbench();
+  logic        clk, reset;
+  logic        a, b, c, s, cout, sexpected, coutexpected;
+  logic [31:0] vectornum, errors;
+  logic [4:0]  testvectors[10000:0];
+
+  // instantiate device under test
+  fulladder dut(a, b, c, s, cout);
+
+  // generate clock
+  always 
+    begin
+      clk = 1; #5; clk = 0; #5;
+    end
+
+  // at start of test, load vectors and pulse reset
+  initial
+    begin
+      $readmemb("fulladder.tv", testvectors);
+      vectornum = 0; errors = 0;
+      reset = 1; #22; reset = 0;
+    end
+
+  // apply test vectors on rising edge of clk
+  always @(posedge clk)
+    begin
+      #1; {a, b, c, coutexpected, sexpected} = testvectors[vectornum];
+    end
+
+  // check results on falling edge of clk
+  always @(negedge clk)
+    if (~reset) begin // skip during reset
+      if (s !== sexpected | cout !== coutexpected) begin  // check result
+        $display("Error: inputs = %b", {a, b, c});
+        $display("  outputs cout s = %b%b (%b%b expected)",cout, s, coutexpected, sexpected);
+        errors = errors + 1;
+      end
+      vectornum = vectornum + 1;
+      if (testvectors[vectornum] === 5'bx) begin 
+        $display("%d tests completed with %d errors", 
+	           vectornum, errors);
+        $stop;
+      end
+    end
+endmodule
+
+module fulladder(input  logic a, b, c,
+                 output logic s, cout);
+
+  assign s = a ^ b ^ c;
+  assign cout = (a & b) | (a & c) | (b & c); 
+endmodule

examples/verilog/fulladder/fulladder.tv

@@ -0,0 +1,8 @@
+000_00
+001_01
+010_01
+011_10
+100_01
+101_10
+110_10
+111_11

pipelined/src/fpu/unpacking.sv

@@ -1,3 +1,5 @@
+`include "wally-config.vh"
+
 module unpacking ( 
     input logic  [63:0] X, Y, Z,
     input logic         FmtE,
@@ -20,6 +22,18 @@ module unpacking (
     logic           XFracZero, YFracZero, ZFracZero; // input fraction zero
     logic           XExpZero, YExpZero, ZExpZero; // input exponent zero
     logic           YExpMaxE, ZExpMaxE;  // input exponent all 1s
+    logic           XDoubleNaN, YDoubleNaN, ZDoubleNaN;
+
+    // Determine if number is NaN as double precision to check single precision NaN boxing
+    if (`XLEN==32) begin
+        assign XDoubleNaN = 1; 
+        assign YDoubleNaN = 1; 
+        assign ZDoubleNaN = 1; 
+    end else begin
+        assign XDoubleNaN = &X[62:52] & |X[51:0]; 
+        assign YDoubleNaN = &Y[62:52] & |Y[51:0]; 
+        assign ZDoubleNaN = &Z[62:52] & |Z[51:0]; 
+    end   
 
     assign XSgnE = FmtE ? X[63] : X[31];
     assign YSgnE = FmtE ? Y[63] : Y[31];
@@ -55,9 +69,10 @@ module unpacking (
   
     assign XNormE = ~(XExpMaxE|XExpZero);
     
-    assign XNaNE = XExpMaxE & ~XFracZero;
-    assign YNaNE = YExpMaxE & ~YFracZero;
-    assign ZNaNE = ZExpMaxE & ~ZFracZero;
+    // force single precision input to be a NaN if it isn't properly Nan Boxed
+    assign XNaNE = XExpMaxE & ~XFracZero | ~FmtE & ~XDoubleNaN;
+    assign YNaNE = YExpMaxE & ~YFracZero | ~FmtE & ~YDoubleNaN;
+    assign ZNaNE = ZExpMaxE & ~ZFracZero | ~FmtE & ~ZDoubleNaN;
 
     assign XSNaNE = XNaNE&~XFracE[51];
     assign YSNaNE = YNaNE&~YFracE[51];

pipelined/src/generic/priorityonehot.sv

@@ -9,7 +9,12 @@
 //              Added working version of parameterized priority encoder. 
 //           David_Harris@Hmc.edu switched to one-hot output
 //
-// Purpose: Priority circuit to choose most significant one-hot output
+// Purpose: Priority circuit producing a 1 in the output in the column where
+//          the least significant 1 appears in the input.
+//
+//  Example:  msb           lsb
+//        in  01011101010100000
+//        out 00000000000100000
 //
 // A component of the Wally configurable RISC-V project.
 //
@@ -30,13 +35,13 @@
 
 `include "wally-config.vh"
 
-module priorityonehot #(parameter ENTRIES = 8) (
-  input  logic  [ENTRIES-1:0] a,
-  output logic  [ENTRIES-1:0] y
+module priorityonehot #(parameter N = 8) (
+  input  logic  [N-1:0] a,
+  output logic  [N-1:0] y
 );
-  logic [ENTRIES-1:0] nolower;
+  logic [N-1:0] nolower;
 
   // create thermometer code mask
-  prioritythermometer #(ENTRIES) maskgen(.a({a[ENTRIES-2:0], 1'b1}), .y(nolower));
+  prioritythermometer #(N) maskgen(.a({a[N-2:0], 1'b0}), .y(nolower));
   assign y = a & nolower;
 endmodule

pipelined/src/generic/prioritythermometer.sv

@@ -1,15 +1,16 @@
 ///////////////////////////////////////////
-// priritythermometer.sv
+// prioritythermometer.sv
 //
 // Written: tfleming@hmc.edu & jtorrey@hmc.edu 7 April 2021
-// Modified: Teo Ene 15 Apr 2021:
-//              Temporarily removed paramterized priority encoder for non-parameterized one
-//              To get synthesis working quickly
-//           Kmacsaigoren@hmc.edu 28 May 2021:
-//              Added working version of parameterized priority encoder. 
 //           David_Harris@Hmc.edu switched to one-hot output
 //
-// Purpose: Priority circuit to choose most significant one-hot output
+// Purpose: Priority circuit producing a thermometer code output.
+//          with 1's in all the least signficant bits of the output
+//          until the column where the least significant 1 occurs in the input.
+//
+//  Example:  msb           lsb
+//        in  01011101010100000
+//        out 00000000000011111
 //
 // A component of the Wally configurable RISC-V project.
 //
@@ -42,7 +43,7 @@ module prioritythermometer #(parameter N = 8) (
 
   // create thermometer code mask
   genvar i;
-  assign y[0] = a[0];
+  assign y[0] = ~a[0];
   for (i=1; i<N; i++) begin:therm
     assign y[i] = y[i-1] & ~a[i];
   end

pipelined/src/ieu/regfile.sv

@@ -45,7 +45,7 @@ module regfile (
     
   always_ff @(negedge clk) // or posedge reset)
     if (reset) for(i=1; i<32; i++) rf[i] <= 0;
-    else if (we3) rf[a3] <= wd3;	
+    else       if (we3)            rf[a3] <= wd3;	
 
   assign #2 rd1 = (a1 != 0) ? rf[a1] : 0;
   assign #2 rd2 = (a2 != 0) ? rf[a2] : 0;

pipelined/src/mmu/tlbram.sv

@@ -40,8 +40,9 @@ module tlbram #(parameter TLB_ENTRIES = 8) (
   logic [`PPN_BITS+9:0] PageTableEntry;
 
   // RAM implemented with array of flops and AND/OR read logic
-  tlbramline #(`PPN_BITS+10) tlblineram[TLB_ENTRIES-1:0](clk, reset, Matches, WriteEnables, PTE[`PPN_BITS+9:0], RamRead, PTE_Gs);
-  //assign PageTableEntry = RamRead.or; // OR each column of RAM read to read PTE
+  tlbramline #(`PPN_BITS+10) tlbramline[TLB_ENTRIES-1:0]
+     (.clk, .reset, .re(Matches), .we(WriteEnables), 
+      .d(PTE[`PPN_BITS+9:0]), .q(RamRead), .PTE_G(PTE_Gs));
   or_rows #(TLB_ENTRIES, `PPN_BITS+10) PTEOr(RamRead, PageTableEntry);
 
   // Rename the bits read from the TLB RAM

pipelined/testbench/tests.vh

@@ -1297,7 +1297,7 @@ string imperas32f[] = '{
     "rv32i_m/F/feq_b1-01", "6220",
     "rv32i_m/F/feq_b19-01", "a190",
     "rv32i_m/F/fle_b1-01", "6220",
-    // "rv32i_m/F/fle_b19-01", "a190", // looks fine to me is the actual input value supposed to be infinity?
+    "rv32i_m/F/fle_b19-01", "a190", // looks fine to me is the actual input value supposed to be infinity?
     "rv32i_m/F/flt_b1-01", "6220",
     "rv32i_m/F/flt_b19-01", "8ee0", 
     "rv32i_m/F/flw-align-01", "2010",
@@ -1323,7 +1323,7 @@ string imperas32f[] = '{
     "rv32i_m/F/fmsub_b15-01", "19bb30",
     "rv32i_m/F/fmsub_b16-01", "39d0",
     "rv32i_m/F/fmsub_b17-01", "39d0",
-    "rv32i_m/F/fmsub_b18-01", "4d20", // test looks fine to me: 7e9db2ee (large number) * -0 - f1bffff8 = f1bffff8 but wants 7f800000 (NaN)
+    "rv32i_m/F/fmsub_b18-01", "4d20", 
     "rv32i_m/F/fmsub_b2-01", "4d60",
     "rv32i_m/F/fmsub_b3-01", "d4f0",
     "rv32i_m/F/fmsub_b4-01", "3700",

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/Makefrag

@@ -28,9 +28,6 @@
 # Description: Makefrag for RV64I architectural tests
 
 rv64i_sc_tests = \
-  add-01 \
-  PIPELINE \
-
 
 
 rv64i_tests = $(addsuffix .elf, $(rv64i_sc_tests))