diff --git a/config/shared/config-shared.vh b/config/shared/config-shared.vh
index 6763f583c..481247eae 100644
--- a/config/shared/config-shared.vh
+++ b/config/shared/config-shared.vh
@@ -1,3 +1,6 @@
+//max function
+`define max(a,b) (((a) > (b)) ? (a) : (b))
+
 // constants defining different privilege modes
 // defined in Table 1.1 of the privileged spec
 localparam M_MODE  = (2'b11);
@@ -107,12 +110,13 @@ localparam DURLEN      = $clog2(FPDUR);                             // enough bi
 localparam DIVBLEN     = $clog2(DIVb+1);                            // enough bits to count number of fractional bits + 1 integer bit
 
 // largest length in IEU/FPU
-localparam CVTLEN = ((NF<XLEN) ? (XLEN) : (NF));  // max(XLEN, NF)
-localparam LLEN = (($unsigned(FLEN)<$unsigned(XLEN)) ? ($unsigned(XLEN)) : ($unsigned(FLEN)));
+localparam BASECVTLEN = `max(XLEN, NF); // convert length excluding Zfa fcvtmod.w.d
+localparam CVTLEN = ZFA_SUPPORTED ? `max(BASECVTLEN, 32'd84) : BASECVTLEN; // fcvtmod.w.d needs at least 32+52 because a double with 52 fractional bits might be into upper bits of 32 bit word
+localparam LLEN = `max($unsigned(FLEN), $unsigned(XLEN));
 localparam LOGCVTLEN = $unsigned($clog2(CVTLEN+1));
-localparam NORMSHIFTSZ = (((CVTLEN+NF+1)>(DIVb + 1 +NF+1) & (CVTLEN+NF+1)>(3*NF+6)) ? (CVTLEN+NF+1) : ((DIVb + 1 +NF+1) > (3*NF+6) ? (DIVb + 1 +NF+1) : (3*NF+6))); // max(CVTLEN+NF+1, DIVb + 1 + NF + 1, 3*NF+6)
+localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1), (DIVb + 1 + NF + 1)), (3*NF+6));
 localparam LOGNORMSHIFTSZ = ($clog2(NORMSHIFTSZ));
-localparam CORRSHIFTSZ = (NORMSHIFTSZ-2 > (DIVMINb + 1 + NF)) ? NORMSHIFTSZ-2 : (DIVMINb+1+NF);  // max(NORMSHIFTSZ-2, DIVMINb + 1 + NF)
+localparam CORRSHIFTSZ = `max((NORMSHIFTSZ-2), (DIVMINb + 1 + NF));
 
 
 // Disable spurious Verilator warnings
diff --git a/sim/wally.do b/sim/wally.do
index 4c1a22074..430146d39 100644
--- a/sim/wally.do
+++ b/sim/wally.do
@@ -33,7 +33,7 @@ vlib work
 # start and run simulation
 # remove +acc flag for faster sim during regressions if there is no need to access internal signals
 if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
-    vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
+    vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
     # start and run simulation
     vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=0 -o testbenchopt 
     vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286  -fatal 7
@@ -47,7 +47,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
     exec ./slack-notifier/slack-notifier.py
     
 } elseif {$2 eq "buildroot-no-trace"} {
-    vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
+    vlog -lint -work work_${1}_${2} +incdir+../config/deriv/$1 +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
     # start and run simulation
     vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_SPOOFING=1 -o testbenchopt 
     vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286  -fatal 7
@@ -68,7 +68,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
 
 } elseif {$2 eq "fpga"} {
     echo "hello"
-    vlog  -work work +incdir+../config/fpga +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/sdc/*.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv  ../../fpga/sim/*.sv -suppress 8852,12070,3084,3829,2583,7063,13286
+    vlog  -work work +incdir+../config/fpga +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/sdc/*.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv  ../../fpga/sim/*.sv -suppress 8852,12070,3084,3829,2583,7063,13286
     vopt +acc work.testbench -G TEST=$2 -G DEBUG=0 -o workopt     
     vsim workopt +nowarn3829  -fatal 7
     
@@ -77,7 +77,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
     run 20 ms
 
 } else {
-    vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 
+    vlog +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 
     vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt 
 
     vsim workopt +nowarn3829  -fatal 7
@@ -103,7 +103,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
 
 
 #elseif {$2 eq "buildroot-no-trace""} {
-#    vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
+#    vlog -lint -work work_${1}_${2} +incdir+../config/deriv/$1 +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
     # start and run simulation
 #    vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=470350800 -G INSTR_WAVEON=470350800 -G CHECKPOINT=470350800 -G DEBUG_TRACE=0 -o testbenchopt 
 #    vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829
diff --git a/src/fpu/postproc/specialcase.sv b/src/fpu/postproc/specialcase.sv
index e3a1466fe..e9ba573e1 100644
--- a/src/fpu/postproc/specialcase.sv
+++ b/src/fpu/postproc/specialcase.sv
@@ -305,7 +305,7 @@ module specialcase import cvw::*;  #(parameter cvw_t P) (
   //          signed | 2^31-1 | 2^63-1 |
   //        unsigned | 2^32-1 | 2^64-1 |
   //
-  //      other: 32 bit unsinged res should be sign extended as if it were a signed number
+  //      other: 32 bit unsigned res should be sign extended as if it were a signed number
 
     if(P.IEEE754) begin   
       always_comb
@@ -343,7 +343,7 @@ module specialcase import cvw::*;  #(parameter cvw_t P) (
         else     OfIntRes2 = OfIntRes;
         if (Zfa) Int64Res = {{(P.XLEN-32){CvtNegRes[P.XLEN-1]}}, CvtNegRes[31:0]};
         else     Int64Res = CvtNegRes[P.XLEN-1:0];
-        if (Zfa) SelCvtOfRes = InfIn | NaNIn  | (CvtCe > 32 + 52); // fcvtmod.w.d only overflows to 0 on NaN or Infinity, or if the shift is so large that only zeros are left
+        if (Zfa) SelCvtOfRes = InfIn | NaNIn | (CvtCe > 32 + 52); // fcvtmod.w.d only overflows to 0 on NaN or Infinity, or if the shift is so large that only zeros are left
         else     SelCvtOfRes = IntInvalid;    // regular fcvt gives an overflow if out of range
     end
   else 
diff --git a/tests/riscof/config.ini b/tests/riscof/config.ini
index ae5a2f13b..961157460 100644
--- a/tests/riscof/config.ini
+++ b/tests/riscof/config.ini
@@ -9,6 +9,9 @@ pluginpath={0}/spike
 ispec={0}/spike/spike_rv{1}_isa.yaml
 pspec={0}/spike/spike_platform.yaml
 target_run=1
+# Optional as mentioned in https://riscof.readthedocs.io/en/latest/inputs.html#config-ini-syntax
+jobs=4
 
 [sail_cSim]
 pluginpath={0}/sail_cSim
+jobs=4
\ No newline at end of file