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Fixed testbench-fp replication length for regression-wally --testfloat. Changed regression-wally to expect -- in named arguments.

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This commit is contained in:
David Harris 2024-04-08 05:57:18 -07:00
parent d182a2925e
commit 60e70c1986
2 changed files with 19 additions and 15 deletions
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28
bin/regression-wally
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@ -254,20 +254,20 @@ os.chdir(regressionDir)
coveragesim = "questa" # Questa is required for code/functional coverage coveragesim = "questa" # Questa is required for code/functional coverage
defaultsim = "questa" # Default simulator for all other tests; change to Verilator when flow is ready defaultsim = "questa" # Default simulator for all other tests; change to Verilator when flow is ready
coverage = '-coverage' in sys.argv coverage = '--coverage' in sys.argv
fp = '-fp' in sys.argv fp = '--fp' in sys.argv
nightly = '-nightly' in sys.argv nightly = '--nightly' in sys.argv
testfloat = '-testfloat' in sys.argv testfloat = '--testfloat' in sys.argv
if (nightly): if (nightly):
nightMode = "-nightly"; nightMode = "--nightly";
sims = ["questa", "verilator", "vcs"] sims = ["questa", "verilator", "vcs"]
else: else:
nightMode = ""; nightMode = "";
sims = [defaultsim] sims = [defaultsim]
if (coverage): # only run RV64GC tests in coverage mode if (coverage): # only run RV64GC tests in coverage mode
coverStr = '-coverage' coverStr = '--coverage'
else: else:
coverStr = '' coverStr = ''
@ -302,6 +302,8 @@ if (testfloat):
testfloatconfigs = ["fdqh_ieee_rv64gc", "fdq_ieee_rv64gc", "fdh_ieee_rv64gc", "fd_ieee_rv64gc", "fh_ieee_rv64gc", "f_ieee_rv64gc", "fdqh_ieee_rv32gc", "f_ieee_rv32gc"] testfloatconfigs = ["fdqh_ieee_rv64gc", "fdq_ieee_rv64gc", "fdh_ieee_rv64gc", "fd_ieee_rv64gc", "fh_ieee_rv64gc", "f_ieee_rv64gc", "fdqh_ieee_rv32gc", "f_ieee_rv32gc"]
for config in testfloatconfigs: for config in testfloatconfigs:
tests = ["div", "sqrt", "add", "sub", "mul", "cvtint", "cvtfp", "fma", "cmp"] tests = ["div", "sqrt", "add", "sub", "mul", "cvtint", "cvtfp", "fma", "cmp"]
if ("f_" in config):
tests.remove("cvtfp")
for test in tests: for test in tests:
tc = TestCase( tc = TestCase(
name=test, name=test,
@ -343,6 +345,8 @@ if (testfloat):
if ("ieee" in config): if ("ieee" in config):
tests.append("cvtint") tests.append("cvtint")
tests.append("cvtfp") tests.append("cvtfp")
if ("f_" in config):
tests.remove("cvtfp")
for test in tests: for test in tests:
tc = TestCase( tc = TestCase(
name=test, name=test,
@ -362,26 +366,26 @@ def main():
except: except:
pass pass
if '-makeTests' in sys.argv: if '--makeTests' in sys.argv:
os.chdir(regressionDir) os.chdir(regressionDir)
os.system('./make-tests.sh | tee ./logs/make-tests.log') os.system('./make-tests.sh | tee ./logs/make-tests.log')
if '-all' in sys.argv: if '--all' in sys.argv:
TIMEOUT_DUR = 30*7200 # seconds TIMEOUT_DUR = 30*7200 # seconds
#configs.append(getBuildrootTC(boot=True)) #configs.append(getBuildrootTC(boot=True))
elif '-buildroot' in sys.argv: elif '--buildroot' in sys.argv:
TIMEOUT_DUR = 30*7200 # seconds TIMEOUT_DUR = 30*7200 # seconds
#configs=[getBuildrootTC(boot=True)] #configs=[getBuildrootTC(boot=True)]
elif '-coverage' in sys.argv: elif '--coverage' in sys.argv:
TIMEOUT_DUR = 20*60 # seconds TIMEOUT_DUR = 20*60 # seconds
# Presently don't run buildroot because it has a different config and can't be merged with the rv64gc coverage. # Presently don't run buildroot because it has a different config and can't be merged with the rv64gc coverage.
# Also it is slow to run. # Also it is slow to run.
# configs.append(getBuildrootTC(boot=False)) # configs.append(getBuildrootTC(boot=False))
os.system('rm -f cov/*.ucdb') os.system('rm -f cov/*.ucdb')
elif '-nightly' in sys.argv: elif '--nightly' in sys.argv:
TIMEOUT_DUR = 60*1440 # 1 day TIMEOUT_DUR = 60*1440 # 1 day
#configs.append(getBuildrootTC(boot=False)) #configs.append(getBuildrootTC(boot=False))
elif '-testfloat' in sys.argv: elif '--testfloat' in sys.argv:
TIMEOUT_DUR = 60*60 # seconds TIMEOUT_DUR = 60*60 # seconds
else: else:
TIMEOUT_DUR = 10*60 # seconds TIMEOUT_DUR = 10*60 # seconds

6
testbench/testbench_fp.sv
View File

@ -1275,7 +1275,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
2'b01: begin // quad -> long 2'b01: begin // quad -> long
X = {TestVector[8+P.XLEN+P.Q_LEN-1:8+(P.XLEN)]}; X = {TestVector[8+P.XLEN+P.Q_LEN-1:8+(P.XLEN)]};
SrcA = {P.XLEN{1'bx}}; SrcA = {P.XLEN{1'bx}};
Ans = {{(P.FLEN-64){1'b0}}, TestVector[8+(P.XLEN-1):8]}; Ans = {{(P.FLEN > 64 ? P.FLEN-64 : 0){1'b0}}, TestVector[8+(P.XLEN-1):8]};
end end
2'b00: begin // quad -> int 2'b00: begin // quad -> int
X = {TestVector[8+32+P.Q_LEN-1:8+(32)]}; X = {TestVector[8+32+P.Q_LEN-1:8+(32)]};
@ -1327,7 +1327,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
2'b01: begin // single -> long 2'b01: begin // single -> long
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.XLEN+P.S_LEN-1:8+(P.XLEN)]}; X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.XLEN+P.S_LEN-1:8+(P.XLEN)]};
SrcA = {P.XLEN{1'bx}}; SrcA = {P.XLEN{1'bx}};
Ans = {{(P.FLEN-64){1'b0}}, TestVector[8+(P.XLEN-1):8]}; Ans = {{(P.FLEN > 64 ? P.FLEN-64 : 0){1'b0}}, TestVector[8+(P.XLEN-1):8]};
end end
2'b00: begin // single -> int 2'b00: begin // single -> int
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+32+P.S_LEN-1:8+(32)]}; X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+32+P.S_LEN-1:8+(32)]};
@ -1353,7 +1353,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
2'b01: begin // half -> long 2'b01: begin // half -> long
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.XLEN+P.H_LEN-1:8+(P.XLEN)]}; X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.XLEN+P.H_LEN-1:8+(P.XLEN)]};
SrcA = {P.XLEN{1'bx}}; SrcA = {P.XLEN{1'bx}};
Ans = {{(P.FLEN-64){1'b0}}, TestVector[8+(P.XLEN-1):8]}; Ans = {{(P.FLEN > 64 ? P.FLEN-64 : 0){1'b0}}, TestVector[8+(P.XLEN-1):8]};
end end
2'b00: begin // half -> int 2'b00: begin // half -> int
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+32+P.H_LEN-1:8+(32)]}; X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+32+P.H_LEN-1:8+(32)]};