HPTW cleanup

pipelined/src/mmu/hptw.sv

@@ -42,7 +42,7 @@ module hptw
    input logic [1:0]           STATUS_MPP,
    input logic [1:0]           PrivilegeModeW,
    (* mark_debug = "true" *) input logic ITLBMissOrDAFaultNoTrapF, DTLBMissOrDAFaultNoTrapM, // TLB Miss
-   input logic [`XLEN-1:0]     HPTWReadPTE, // page table entry from LSU
+   input logic [`XLEN-1:0]     HPTWReadPTE, // page table entry from LSU  *** change to ReadDataM
    input logic                 DCacheStallM, // stall from LSU
    output logic [`XLEN-1:0]    PTE, // page table entry to TLBs
    output logic [1:0]          PageType, // page type to TLBs
@@ -106,7 +106,6 @@ module hptw
 
   if(`HPTW_WRITES_SUPPORTED) begin : hptwwrites
 
-    logic                     SV39Mode;
     logic                     ReadAccess, WriteAccess;
     logic                     InvalidRead, InvalidWrite;
     logic                     UpperBitsUnequalPageFault; 
@@ -136,19 +135,9 @@ module hptw
     assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) |
                                ((EffectivePrivilegeMode == `S_MODE) & PTE_U & (~STATUS_SUM & DTLBWalk));
 
-    // *** turn into module common with code in tlbcontrol.
+    // Check for page faults
-    if (`XLEN==64) begin:rv64
+	vm64check vm64check(.SATP_MODE(SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]), .VAdr(TranslationVAdr), 
-      assign SV39Mode = (SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS] == `SV39);
+	                               .SV39Mode(), .UpperBitsUnequalPageFault);
-      // page fault if upper bits aren't all the same
-      logic UpperEqual39, UpperEqual48;
-      assign UpperEqual39 = &(TranslationVAdr[63:38]) | ~|(TranslationVAdr[63:38]);
-      assign UpperEqual48 = &(TranslationVAdr[63:47]) | ~|(TranslationVAdr[63:47]); 
-      assign UpperBitsUnequalPageFault = SV39Mode ? ~UpperEqual39 : ~UpperEqual48;
-    end else begin
-      assign SV39Mode = 0;
-      assign UpperBitsUnequalPageFault = 0;
-    end           
-
     assign InvalidRead = ReadAccess & ~Readable & (~STATUS_MXR | ~Executable);
     assign InvalidWrite = WriteAccess & ~Writable;
     assign OtherPageFault = DTLBWalk? ImproperPrivilege | InvalidRead | InvalidWrite | UpperBitsUnequalPageFault | Misaligned | ~Valid :
@@ -228,11 +217,6 @@ module hptw
 	end
 
 	// Page Table Walker FSM
-	// If the setup time on the D$ RAM is short, it should be possible to merge the LEVELx_READ and LEVELx states
-	// to decrease the latency of the HPTW.  However, if the D$ is a cycle limiter, it's better to leave the
-	// HPTW as shown below to keep the D$ setup time out of the critical path.
-	// *** Is this really true.  Talk with Ross.  Seems like it's the next state logic on critical path instead.
-	// *** address TYPE(statetype)
 	flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); 
 	always_comb 
 		case (WalkerState)
@@ -241,20 +225,16 @@ module hptw
 			L3_ADR:                     								NextWalkerState = L3_RD; // first access in SV48
 			L3_RD: if (DCacheStallM)    								NextWalkerState = L3_RD;
 				   else     											NextWalkerState = L2_ADR;
-	L2_ADR: if (InitialWalkerState == L2_ADR)    NextWalkerState = L2_RD; // first access in SV39
+			L2_ADR: if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // first access in SV39
-			else if (ValidLeafPTE & ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
-			else if (ValidNonLeafPTE)            NextWalkerState = L2_RD;
 					else 				                 				NextWalkerState = LEAF;
 			L2_RD: if (DCacheStallM)                     				NextWalkerState = L2_RD;
 				else                                     				NextWalkerState = L1_ADR;
-	L1_ADR: if (InitialWalkerState == L1_ADR)    NextWalkerState = L1_RD; // first access in SV32
+			L1_ADR: if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // first access in SV32
-			else if (ValidLeafPTE & ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
 					else if (ValidNonLeafPTE)            				NextWalkerState = L1_RD;
 					else 				                				NextWalkerState = LEAF;	
 			L1_RD: if (DCacheStallM)                     				NextWalkerState = L1_RD;
 				else                                     				NextWalkerState = L0_ADR;
-	L0_ADR: if (ValidLeafPTE & ~Misaligned)      NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
+			L0_ADR: if (ValidNonLeafPTE)                 				NextWalkerState = L0_RD;
-			else if (ValidNonLeafPTE)            NextWalkerState = L0_RD;
 					else                                 				NextWalkerState = LEAF;
 			L0_RD: if (DCacheStallM)                     				NextWalkerState = L0_RD;
 				   else                                     			NextWalkerState = LEAF;
@@ -262,9 +242,7 @@ module hptw
 				  else 													NextWalkerState = IDLE;
 			UPDATE_PTE: if(`HPTW_WRITES_SUPPORTED & DCacheStallM) 		NextWalkerState = UPDATE_PTE;
 						else 											NextWalkerState = LEAF;
-	default: begin
+			default: 													NextWalkerState = IDLE; // should never be reached
-		NextWalkerState = IDLE; // should never be reached
-	end
 		endcase // case (WalkerState)
 
   assign IgnoreRequestTLB = WalkerState == IDLE & TLBMiss;

pipelined/src/mmu/tlbcontrol.sv

@@ -68,22 +68,12 @@ module tlbcontrol #(parameter ITLB = 0) (
   // Grab the sv mode from SATP and determine whether translation should occur
   assign EffectivePrivilegeMode = (ITLB == 1) ? PrivilegeModeW : (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW); // DTLB uses MPP mode when MPRV is 1
   assign Translate = (SATP_MODE != `NO_TRANSLATE) & (EffectivePrivilegeMode != `M_MODE) & ~DisableTranslation; 
-  if (`XLEN==64) begin:rv64
-      assign SV39Mode = (SATP_MODE == `SV39);
-      // page fault if upper bits aren't all the same
-      logic UpperEqual39, UpperEqual48;
-      assign UpperEqual39 = &(VAdr[63:38]) | ~|(VAdr[63:38]);
-      assign UpperEqual48 = &(VAdr[63:47]) | ~|(VAdr[63:47]); 
-      assign UpperBitsUnequalPageFault = SV39Mode ? ~UpperEqual39 : ~UpperEqual48;
-  end else begin
-      assign SV39Mode = 0;
-      assign UpperBitsUnequalPageFault = 0;
-  end           
 
   // Determine whether TLB is being used
   assign TLBAccess = ReadAccess | WriteAccess;
 
   // Check whether upper bits of virtual addresss are all equal
+  vm64check vm64check(.SATP_MODE, .VAdr, .SV39Mode, .UpperBitsUnequalPageFault);
 
   // unswizzle useful PTE bits
   assign {PTE_D, PTE_A} = PTEAccessBits[7:6];

pipelined/src/mmu/vm64check.sv

@@ -0,0 +1,50 @@
+///////////////////////////////////////////
+// vm64check.sv
+//
+// Written: David_Harris@hmc.edu 4 November 2022
+// Modified: 
+//
+// Purpose: Check for good upper address bits in RV64 mode
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// MIT LICENSE
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
+// software and associated documentation files (the "Software"), to deal in the Software 
+// without restriction, including without limitation the rights to use, copy, modify, merge, 
+// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
+// to whom the Software is furnished to do so, subject to the following conditions:
+//
+//   The above copyright notice and this permission notice shall be included in all copies or 
+//   substantial portions of the Software.
+//
+//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+//   OR OTHER DEALINGS IN THE SOFTWARE.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module vm64check (
+   input  logic [`SVMODE_BITS-1:0] SATP_MODE,
+   input  logic [`XLEN-1:0]        VAdr,
+   output logic                    SV39Mode, UpperBitsUnequalPageFault
+);
+
+  if (`XLEN==64) begin:rv64
+      assign SV39Mode = (SATP_MODE == `SV39);
+      // page fault if upper bits aren't all the same
+      logic UpperEqual39, UpperEqual48;
+      assign UpperEqual39 = &(VAdr[63:38]) | ~|(VAdr[63:38]);
+      assign UpperEqual48 = &(VAdr[63:47]) | ~|(VAdr[63:47]); 
+      assign UpperBitsUnequalPageFault = SV39Mode ? ~UpperEqual39 : ~UpperEqual48;
+  end else begin
+      assign SV39Mode = 0;
+      assign UpperBitsUnequalPageFault = 0;
+  end           
+endmodule