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HPTW cleanup
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@ -42,7 +42,7 @@ module hptw
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input logic [1:0] STATUS_MPP,
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input logic [1:0] STATUS_MPP,
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input logic [1:0] PrivilegeModeW,
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input logic [1:0] PrivilegeModeW,
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(* mark_debug = "true" *) input logic ITLBMissOrDAFaultNoTrapF, DTLBMissOrDAFaultNoTrapM, // TLB Miss
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(* mark_debug = "true" *) input logic ITLBMissOrDAFaultNoTrapF, DTLBMissOrDAFaultNoTrapM, // TLB Miss
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input logic [`XLEN-1:0] HPTWReadPTE, // page table entry from LSU
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input logic [`XLEN-1:0] HPTWReadPTE, // page table entry from LSU *** change to ReadDataM
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input logic DCacheStallM, // stall from LSU
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input logic DCacheStallM, // stall from LSU
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output logic [`XLEN-1:0] PTE, // page table entry to TLBs
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output logic [`XLEN-1:0] PTE, // page table entry to TLBs
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output logic [1:0] PageType, // page type to TLBs
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output logic [1:0] PageType, // page type to TLBs
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@ -106,7 +106,6 @@ module hptw
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if(`HPTW_WRITES_SUPPORTED) begin : hptwwrites
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if(`HPTW_WRITES_SUPPORTED) begin : hptwwrites
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logic SV39Mode;
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logic ReadAccess, WriteAccess;
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logic ReadAccess, WriteAccess;
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logic InvalidRead, InvalidWrite;
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logic InvalidRead, InvalidWrite;
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logic UpperBitsUnequalPageFault;
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logic UpperBitsUnequalPageFault;
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@ -136,19 +135,9 @@ module hptw
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assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) |
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assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) |
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((EffectivePrivilegeMode == `S_MODE) & PTE_U & (~STATUS_SUM & DTLBWalk));
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((EffectivePrivilegeMode == `S_MODE) & PTE_U & (~STATUS_SUM & DTLBWalk));
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// *** turn into module common with code in tlbcontrol.
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// Check for page faults
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if (`XLEN==64) begin:rv64
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vm64check vm64check(.SATP_MODE(SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]), .VAdr(TranslationVAdr),
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assign SV39Mode = (SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS] == `SV39);
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.SV39Mode(), .UpperBitsUnequalPageFault);
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// page fault if upper bits aren't all the same
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logic UpperEqual39, UpperEqual48;
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assign UpperEqual39 = &(TranslationVAdr[63:38]) | ~|(TranslationVAdr[63:38]);
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assign UpperEqual48 = &(TranslationVAdr[63:47]) | ~|(TranslationVAdr[63:47]);
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assign UpperBitsUnequalPageFault = SV39Mode ? ~UpperEqual39 : ~UpperEqual48;
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end else begin
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assign SV39Mode = 0;
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assign UpperBitsUnequalPageFault = 0;
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end
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assign InvalidRead = ReadAccess & ~Readable & (~STATUS_MXR | ~Executable);
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assign InvalidRead = ReadAccess & ~Readable & (~STATUS_MXR | ~Executable);
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assign InvalidWrite = WriteAccess & ~Writable;
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assign InvalidWrite = WriteAccess & ~Writable;
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assign OtherPageFault = DTLBWalk? ImproperPrivilege | InvalidRead | InvalidWrite | UpperBitsUnequalPageFault | Misaligned | ~Valid :
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assign OtherPageFault = DTLBWalk? ImproperPrivilege | InvalidRead | InvalidWrite | UpperBitsUnequalPageFault | Misaligned | ~Valid :
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@ -228,11 +217,6 @@ module hptw
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end
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end
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// Page Table Walker FSM
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// Page Table Walker FSM
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// If the setup time on the D$ RAM is short, it should be possible to merge the LEVELx_READ and LEVELx states
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// to decrease the latency of the HPTW. However, if the D$ is a cycle limiter, it's better to leave the
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// HPTW as shown below to keep the D$ setup time out of the critical path.
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// *** Is this really true. Talk with Ross. Seems like it's the next state logic on critical path instead.
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// *** address TYPE(statetype)
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flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
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flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
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always_comb
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always_comb
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case (WalkerState)
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case (WalkerState)
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@ -241,20 +225,16 @@ module hptw
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L3_ADR: NextWalkerState = L3_RD; // first access in SV48
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L3_ADR: NextWalkerState = L3_RD; // first access in SV48
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L3_RD: if (DCacheStallM) NextWalkerState = L3_RD;
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L3_RD: if (DCacheStallM) NextWalkerState = L3_RD;
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else NextWalkerState = L2_ADR;
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else NextWalkerState = L2_ADR;
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L2_ADR: if (InitialWalkerState == L2_ADR) NextWalkerState = L2_RD; // first access in SV39
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L2_ADR: if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // first access in SV39
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else if (ValidLeafPTE & ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
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else if (ValidNonLeafPTE) NextWalkerState = L2_RD;
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else NextWalkerState = LEAF;
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else NextWalkerState = LEAF;
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L2_RD: if (DCacheStallM) NextWalkerState = L2_RD;
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L2_RD: if (DCacheStallM) NextWalkerState = L2_RD;
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else NextWalkerState = L1_ADR;
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else NextWalkerState = L1_ADR;
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L1_ADR: if (InitialWalkerState == L1_ADR) NextWalkerState = L1_RD; // first access in SV32
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L1_ADR: if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // first access in SV32
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else if (ValidLeafPTE & ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
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else if (ValidNonLeafPTE) NextWalkerState = L1_RD;
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else if (ValidNonLeafPTE) NextWalkerState = L1_RD;
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else NextWalkerState = LEAF;
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else NextWalkerState = LEAF;
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L1_RD: if (DCacheStallM) NextWalkerState = L1_RD;
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L1_RD: if (DCacheStallM) NextWalkerState = L1_RD;
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else NextWalkerState = L0_ADR;
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else NextWalkerState = L0_ADR;
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L0_ADR: if (ValidLeafPTE & ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
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L0_ADR: if (ValidNonLeafPTE) NextWalkerState = L0_RD;
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else if (ValidNonLeafPTE) NextWalkerState = L0_RD;
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else NextWalkerState = LEAF;
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else NextWalkerState = LEAF;
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L0_RD: if (DCacheStallM) NextWalkerState = L0_RD;
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L0_RD: if (DCacheStallM) NextWalkerState = L0_RD;
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else NextWalkerState = LEAF;
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else NextWalkerState = LEAF;
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@ -262,9 +242,7 @@ module hptw
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else NextWalkerState = IDLE;
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else NextWalkerState = IDLE;
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UPDATE_PTE: if(`HPTW_WRITES_SUPPORTED & DCacheStallM) NextWalkerState = UPDATE_PTE;
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UPDATE_PTE: if(`HPTW_WRITES_SUPPORTED & DCacheStallM) NextWalkerState = UPDATE_PTE;
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else NextWalkerState = LEAF;
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else NextWalkerState = LEAF;
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default: begin
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default: NextWalkerState = IDLE; // should never be reached
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NextWalkerState = IDLE; // should never be reached
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end
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endcase // case (WalkerState)
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endcase // case (WalkerState)
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assign IgnoreRequestTLB = WalkerState == IDLE & TLBMiss;
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assign IgnoreRequestTLB = WalkerState == IDLE & TLBMiss;
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@ -68,22 +68,12 @@ module tlbcontrol #(parameter ITLB = 0) (
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// Grab the sv mode from SATP and determine whether translation should occur
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// Grab the sv mode from SATP and determine whether translation should occur
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assign EffectivePrivilegeMode = (ITLB == 1) ? PrivilegeModeW : (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW); // DTLB uses MPP mode when MPRV is 1
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assign EffectivePrivilegeMode = (ITLB == 1) ? PrivilegeModeW : (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW); // DTLB uses MPP mode when MPRV is 1
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assign Translate = (SATP_MODE != `NO_TRANSLATE) & (EffectivePrivilegeMode != `M_MODE) & ~DisableTranslation;
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assign Translate = (SATP_MODE != `NO_TRANSLATE) & (EffectivePrivilegeMode != `M_MODE) & ~DisableTranslation;
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if (`XLEN==64) begin:rv64
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assign SV39Mode = (SATP_MODE == `SV39);
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// page fault if upper bits aren't all the same
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logic UpperEqual39, UpperEqual48;
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assign UpperEqual39 = &(VAdr[63:38]) | ~|(VAdr[63:38]);
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assign UpperEqual48 = &(VAdr[63:47]) | ~|(VAdr[63:47]);
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assign UpperBitsUnequalPageFault = SV39Mode ? ~UpperEqual39 : ~UpperEqual48;
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end else begin
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assign SV39Mode = 0;
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assign UpperBitsUnequalPageFault = 0;
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end
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// Determine whether TLB is being used
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// Determine whether TLB is being used
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assign TLBAccess = ReadAccess | WriteAccess;
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assign TLBAccess = ReadAccess | WriteAccess;
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// Check whether upper bits of virtual addresss are all equal
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// Check whether upper bits of virtual addresss are all equal
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vm64check vm64check(.SATP_MODE, .VAdr, .SV39Mode, .UpperBitsUnequalPageFault);
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// unswizzle useful PTE bits
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// unswizzle useful PTE bits
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assign {PTE_D, PTE_A} = PTEAccessBits[7:6];
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assign {PTE_D, PTE_A} = PTEAccessBits[7:6];
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50
pipelined/src/mmu/vm64check.sv
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50
pipelined/src/mmu/vm64check.sv
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@ -0,0 +1,50 @@
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///////////////////////////////////////////
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// vm64check.sv
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//
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// Written: David_Harris@hmc.edu 4 November 2022
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// Modified:
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//
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// Purpose: Check for good upper address bits in RV64 mode
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module vm64check (
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input logic [`SVMODE_BITS-1:0] SATP_MODE,
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input logic [`XLEN-1:0] VAdr,
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output logic SV39Mode, UpperBitsUnequalPageFault
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);
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if (`XLEN==64) begin:rv64
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assign SV39Mode = (SATP_MODE == `SV39);
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// page fault if upper bits aren't all the same
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logic UpperEqual39, UpperEqual48;
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assign UpperEqual39 = &(VAdr[63:38]) | ~|(VAdr[63:38]);
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assign UpperEqual48 = &(VAdr[63:47]) | ~|(VAdr[63:47]);
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assign UpperBitsUnequalPageFault = SV39Mode ? ~UpperEqual39 : ~UpperEqual48;
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end else begin
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assign SV39Mode = 0;
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assign UpperBitsUnequalPageFault = 0;
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end
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endmodule
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