Progress on LSU.

src/lsu/amoalu.sv

@@ -27,17 +27,15 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
+module amoalu import cvw::*;  #(parameter cvw_t P) (
-
+  input  logic [P.XLEN-1:0] ReadDataM,    // LSU's ReadData
-module amoalu (
+  input  logic [P.XLEN-1:0] IHWriteDataM, // LSU's WriteData
-  input  logic [`XLEN-1:0] ReadDataM,    // LSU's ReadData
-  input  logic [`XLEN-1:0] IHWriteDataM, // LSU's WriteData
   input  logic [6:0]       LSUFunct7M,   // ALU Operation
   input  logic [2:0]       LSUFunct3M,   // Memoy access width
-  output logic [`XLEN-1:0] AMOResultM    // ALU output
+  output logic [P.XLEN-1:0] AMOResultM    // ALU output
 );
 
-  logic [`XLEN-1:0] a, b, y;
+  logic [P.XLEN-1:0] a, b, y;
 
   // *** see how synthesis generates this and optimize more structurally if necessary to share hardware
   // a single carry chain should be shared for + and the four min/max
@@ -53,15 +51,15 @@ module amoalu (
       5'b10100: y = ($signed(a) >= $signed(b)) ? a : b;     // amomax
       5'b11000: y = ($unsigned(a) < $unsigned(b)) ? a : b;  // amominu
       5'b11100: y = ($unsigned(a) >= $unsigned(b)) ? a : b; // amomaxu
-      default:  y = `XLEN'bx;                               // undefined; *** could change to b for efficiency
+      default:  y = 'x;                                     // undefined; *** could change to b for efficiency
     endcase
 
   // sign extend if necessary
-  if (`XLEN == 32) begin:sext
+  if (P.XLEN == 32) begin:sext
     assign a = ReadDataM;
     assign b = IHWriteDataM;
     assign AMOResultM = y;
-  end else begin:sext // `XLEN = 64
+  end else begin:sext // P.XLEN = 64
     always_comb 
       if (LSUFunct3M[1:0] == 2'b10) begin // sign-extend word-length operations
         a = {{32{ReadDataM[31]}}, ReadDataM[31:0]};

src/lsu/atomic.sv

@@ -27,31 +27,29 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
+module atomic import cvw::*;  #(parameter cvw_t P) (
-
-module atomic (
   input logic                clk,
   input logic                reset, 
   input logic                StallW,
-  input logic [`XLEN-1:0]    ReadDataM,      // LSU ReadData XLEN because FPU does not issue atomic memory operation from FPU registers
+  input logic [P.XLEN-1:0]    ReadDataM,      // LSU ReadData XLEN because FPU does not issue atomic memory operation from FPU registers
-  input logic [`XLEN-1:0]    IHWriteDataM,   // LSU WriteData XLEN because FPU does not issue atomic memory operation from FPU registers
+  input logic [P.XLEN-1:0]    IHWriteDataM,   // LSU WriteData XLEN because FPU does not issue atomic memory operation from FPU registers
-  input logic [`PA_BITS-1:0] PAdrM,          // Physical memory address
+  input logic [P.PA_BITS-1:0] PAdrM,          // Physical memory address
   input logic [6:0]          LSUFunct7M,     // AMO alu operation gated by HPTW
   input logic [2:0]          LSUFunct3M,     // IEU or HPTW memory operation size
   input logic [1:0]          LSUAtomicM,     // 10: AMO operation, select AMOResultM as the writedata output, 01: LR/SC operation
   input logic [1:0]          PreLSURWM,      // IEU or HPTW Read/Write signal
   input logic                IgnoreRequest,  // On FlushM or TLB miss ignore memory operation
-  output logic [`XLEN-1:0]   IMAWriteDataM,  // IEU, HPTW, or AMO write data
+  output logic [P.XLEN-1:0]   IMAWriteDataM,  // IEU, HPTW, or AMO write data
   output logic               SquashSCW,      // Store conditional failed disable write to GPR
   output logic [1:0]         LSURWM          // IEU or HPTW Read/Write signal gated by LR/SC
 );
 
-  logic [`XLEN-1:0]          AMOResultM;
+  logic [P.XLEN-1:0]          AMOResultM;
   logic                      MemReadM;
 
-  amoalu amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResultM);
+  amoalu #(P) amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResultM);
 
-  mux2 #(`XLEN) wdmux(IHWriteDataM, AMOResultM, LSUAtomicM[1], IMAWriteDataM);
+  mux2 #(P.XLEN) wdmux(IHWriteDataM, AMOResultM, LSUAtomicM[1], IMAWriteDataM);
   assign MemReadM = PreLSURWM[1] & ~IgnoreRequest;
 
   lrsc lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM);

src/lsu/dtim.sv

@@ -29,29 +29,29 @@
 
 `include "wally-config.vh"
 
-module dtim(
+module dtim import cvw::*;  #(parameter cvw_t P) (
   input logic                clk, 
   input logic                FlushW,        
   input logic                ce,            // Chip Enable.  0: Holds ReadDataWordM
   input logic [1:0]          MemRWM,        // Read/Write control
-  input logic [`PA_BITS-1:0] DTIMAdr,       // No stall: Execution stage memory address. Stall: Memory stage memory address
+  input logic [P.PA_BITS-1:0] DTIMAdr,       // No stall: Execution stage memory address. Stall: Memory stage memory address
-  input logic [`LLEN-1:0]    WriteDataM,    // Write data from IEU
+  input logic [P.LLEN-1:0]    WriteDataM,    // Write data from IEU
-  input logic [`LLEN/8-1:0]  ByteMaskM,     // Selects which bytes within a word to write
+  input logic [P.LLEN/8-1:0]  ByteMaskM,     // Selects which bytes within a word to write
-  output logic [`LLEN-1:0]   ReadDataWordM  // Read data before subword selection
+  output logic [P.LLEN-1:0]   ReadDataWordM  // Read data before subword selection
   );
 
   logic                      we;
  
-  localparam LLENBYTES  = `LLEN/8;
+  localparam LLENBYTES  = P.LLEN/8;
   // verilator  lint_off WIDTH 
-  localparam DEPTH      = `DTIM_RANGE/LLENBYTES;
+  localparam DEPTH      = P.DTIM_RANGE/LLENBYTES;
   // verilator  lint_on WIDTH 
   localparam ADDR_WDITH = $clog2(DEPTH);
   localparam OFFSET     = $clog2(LLENBYTES);
 
   assign we = MemRWM[0]  & ~FlushW;  // have to ignore write if Trap.
 
-  ram1p1rwbe #(.DEPTH(DEPTH), .WIDTH(`LLEN)) 
+  ram1p1rwbe #(.DEPTH(DEPTH), .WIDTH(P.LLEN)) 
     ram(.clk, .ce, .we, .bwe(ByteMaskM), .addr(DTIMAdr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM));
 endmodule  
   

src/lsu/endianswap.sv

@@ -29,7 +29,7 @@
 
 `include "wally-config.vh"
 
-module endianswap #(parameter LEN=`XLEN) (
+module endianswap #(parameter LEN) (
   input  logic            BigEndianM,
   input  logic [LEN-1:0]  a,
   output logic [LEN-1:0]  y

src/lsu/lsu.sv

@@ -229,7 +229,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
     assign DTIMMemRWM = SelDTIM & ~IgnoreRequestTLB ? LSURWM : '0;
     // **** fix ReadDataWordM to be LLEN. ByteMask is wrong length.
     // **** create config to support DTIM with floating point.
-    dtim dtim(.clk, .ce(~GatedStallW), .MemRWM(DTIMMemRWM),
+    dtim #(P) dtim(.clk, .ce(~GatedStallW), .MemRWM(DTIMMemRWM),
               .DTIMAdr, .FlushW, .WriteDataM(LSUWriteDataM), 
               .ReadDataWordM(DTIMReadDataWordM[P.XLEN-1:0]), .ByteMaskM(ByteMaskM[P.XLEN/8-1:0]));
   end else begin
@@ -321,7 +321,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
   // Atomic operations
   /////////////////////////////////////////////////////////////////////////////////////////////
   if (P.A_SUPPORTED) begin:atomic
-    atomic atomic(.clk, .reset, .StallW, .ReadDataM(ReadDataM[P.XLEN-1:0]), .IHWriteDataM, .PAdrM, 
+    atomic #(P) atomic(.clk, .reset, .StallW, .ReadDataM(ReadDataM[P.XLEN-1:0]), .IHWriteDataM, .PAdrM, 
       .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest, 
       .IMAWriteDataM, .SquashSCW, .LSURWM);
   end else begin:lrsc