From 4acac083205909ddfe4137402ab8758549cd20fb Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Fri, 30 Aug 2024 14:17:37 -0500 Subject: [PATCH] Fixed Arty constraints and corrected typos. --- fpga/constraints/constraints-ArtyA7.xdc | 166 ++++++++++++------------ 1 file changed, 83 insertions(+), 83 deletions(-) diff --git a/fpga/constraints/constraints-ArtyA7.xdc b/fpga/constraints/constraints-ArtyA7.xdc index 7eb3598f5..924cd1aea 100644 --- a/fpga/constraints/constraints-ArtyA7.xdc +++ b/fpga/constraints/constraints-ArtyA7.xdc @@ -4,7 +4,7 @@ # This clock is not used by wally or the AHB Bus. However it is used by the AXI BUS on the DD3 IP. #create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O] -create_generated_clock -name SPISDCClock -source [get_pins clk_out3_xlnx_mmcm] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncore.uncore/sdc.sdc/SPICLK] +create_generated_clock -name SPISDCClock -source [get_pins mmcm/clk_out3] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SPICLK] ##### clock ##### set_property PACKAGE_PIN E3 [get_ports default_100mhz_clk] @@ -45,8 +45,8 @@ set_property IOSTANDARD LVCMOS33 [get_ports {GPI[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {GPI[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {GPI[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {GPI[0]}] -set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 0.000 [get_ports {GPI[*]}] -set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [get_ports {GPI[*]}] +set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports {GPI[*]}] +set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports {GPI[*]}] set_max_delay -from [get_ports {GPI[*]}] 20.000 ##### GPO #### @@ -62,8 +62,8 @@ set_property IOSTANDARD LVCMOS33 [get_ports {GPO[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {GPO[0]}] set_max_delay -to [get_ports {GPO[*]}] 20.000 -set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 0.000 [get_ports {GPO[*]}] -set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [get_ports {GPO[*]}] +set_output_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports {GPO[*]}] +set_output_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports {GPO[*]}] ##### UART ##### @@ -75,24 +75,24 @@ set_max_delay -to [get_ports UARTSout] 20.000 set_property IOSTANDARD LVCMOS33 [get_ports UARTSin] set_property IOSTANDARD LVCMOS33 [get_ports UARTSout] set_property DRIVE 4 [get_ports UARTSout] -set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 0.000 [get_ports UARTSin] -set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [get_ports UARTSin] -set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 0.000 [get_ports UARTSout] -set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [get_ports UARTSout] +set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports UARTSin] +set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports UARTSin] +set_output_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports UARTSout] +set_output_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports UARTSout] ##### reset ##### #************** reset is inverted -set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [get_ports resetn] -set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports resetn] +set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 2.000 [get_ports resetn] +set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 2.000 [get_ports resetn] set_max_delay -from [get_ports resetn] 20.000 set_false_path -from [get_ports resetn] set_property PACKAGE_PIN C2 [get_ports resetn] set_property IOSTANDARD LVCMOS33 [get_ports resetn] -set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [get_ports south_reset] -set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports south_reset] +set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 2.000 [get_ports south_reset] +set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 2.000 [get_ports south_reset] set_max_delay -from [get_ports south_reset] 20.000 set_false_path -from [get_ports south_reset] set_property PACKAGE_PIN D9 [get_ports south_reset] @@ -220,77 +220,77 @@ set_property IOSTANDARD SSTL135 [get_ports {ddr3_odt[0]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_cs_n[0]}] -set_properity PACKAGE_PIN K5 [get_ports ddr3_dq[0]] -set_properity PACKAGE_PIN L3 [get_ports ddr3_dq[1]] -set_properity PACKAGE_PIN K3 [get_ports ddr3_dq[2]] -set_properity PACKAGE_PIN L6 [get_ports ddr3_dq[3]] -set_properity PACKAGE_PIN M3 [get_ports ddr3_dq[4]] -set_properity PACKAGE_PIN M1 [get_ports ddr3_dq[5]] -set_properity PACKAGE_PIN L4 [get_ports ddr3_dq[6]] -set_properity PACKAGE_PIN M2 [get_ports ddr3_dq[7]] -set_properity PACKAGE_PIN V4 [get_ports ddr3_dq[8]] -set_properity PACKAGE_PIN T5 [get_ports ddr3_dq[9]] -set_properity PACKAGE_PIN U4 [get_ports ddr3_dq[10]] -set_properity PACKAGE_PIN V5 [get_ports ddr3_dq[11]] -set_properity PACKAGE_PIN V1 [get_ports ddr3_dq[12]] -set_properity PACKAGE_PIN T3 [get_ports ddr3_dq[13]] -set_properity PACKAGE_PIN U3 [get_ports ddr3_dq[14]] -set_properity PACKAGE_PIN R3 [get_ports ddr3_dq[15]] -set_properity PACKAGE_PIN L1 [get_ports ddr3_dm[0]] -set_properity PACKAGE_PIN U1 [get_ports ddr3_dm[1]] -set_properity PACKAGE_PIN N2 [get_ports ddr3_dqs_p[0]] -set_properity PACKAGE_PIN N1 [get_ports ddr3_dqs_n[0]] -set_properity PACKAGE_PIN U2 [get_ports ddr3_dqs_p[1]] -set_properity PACKAGE_PIN V2 [get_ports ddr3_dqs_n[1]] -set_properity PACKAGE_PIN T8 [get_ports ddr3_addr[13]] -set_properity PACKAGE_PIN T6 [get_ports ddr3_addr[12]] -set_properity PACKAGE_PIN U6 [get_ports ddr3_addr[11]] -set_properity PACKAGE_PIN R6 [get_ports ddr3_addr[10]] -set_properity PACKAGE_PIN V7 [get_ports ddr3_addr[9]] -set_properity PACKAGE_PIN R8 [get_ports ddr3_addr[8]] -set_properity PACKAGE_PIN U7 [get_ports ddr3_addr[7]] -set_properity PACKAGE_PIN V6 [get_ports ddr3_addr[6]] -set_properity PACKAGE_PIN R7 [get_ports ddr3_addr[5]] -set_properity PACKAGE_PIN N6 [get_ports ddr3_addr[4]] -set_properity PACKAGE_PIN T1 [get_ports ddr3_addr[3]] -set_properity PACKAGE_PIN N4 [get_ports ddr3_addr[2]] -set_properity PACKAGE_PIN M6 [get_ports ddr3_addr[1]] -set_properity PACKAGE_PIN R2 [get_ports ddr3_addr[0]] -set_properity PACKAGE_PIN P2 [get_ports ddr3_ba[2]] -set_properity PACKAGE_PIN P4 [get_ports ddr3_ba[1]] -set_properity PACKAGE_PIN R1 [get_ports ddr3_ba[0]] -set_properity PACKAGE_PIN U9 [get_ports ddr3_ck_p[0]] -set_properity PACKAGE_PIN V9 [get_ports ddr3_ck_n[0]] -set_properity PACKAGE_PIN P3 [get_ports ddr3_ras_n] -set_properity PACKAGE_PIN M4 [get_ports ddr3_cas_n] -set_properity PACKAGE_PIN P5 [get_ports ddr3_we_n] -set_properity PACKAGE_PIN K6 [get_ports ddr3_reset_n] -set_properity PACKAGE_PIN N5 [get_ports ddr3_cke[0]] -set_properity PACKAGE_PIN R5 [get_ports ddr3_odt[0]] -set_properity PACKAGE_PIN U8 [get_ports ddr3_cs_n[0]] +set_property PACKAGE_PIN K5 [get_ports ddr3_dq[0]] +set_property PACKAGE_PIN L3 [get_ports ddr3_dq[1]] +set_property PACKAGE_PIN K3 [get_ports ddr3_dq[2]] +set_property PACKAGE_PIN L6 [get_ports ddr3_dq[3]] +set_property PACKAGE_PIN M3 [get_ports ddr3_dq[4]] +set_property PACKAGE_PIN M1 [get_ports ddr3_dq[5]] +set_property PACKAGE_PIN L4 [get_ports ddr3_dq[6]] +set_property PACKAGE_PIN M2 [get_ports ddr3_dq[7]] +set_property PACKAGE_PIN V4 [get_ports ddr3_dq[8]] +set_property PACKAGE_PIN T5 [get_ports ddr3_dq[9]] +set_property PACKAGE_PIN U4 [get_ports ddr3_dq[10]] +set_property PACKAGE_PIN V5 [get_ports ddr3_dq[11]] +set_property PACKAGE_PIN V1 [get_ports ddr3_dq[12]] +set_property PACKAGE_PIN T3 [get_ports ddr3_dq[13]] +set_property PACKAGE_PIN U3 [get_ports ddr3_dq[14]] +set_property PACKAGE_PIN R3 [get_ports ddr3_dq[15]] +set_property PACKAGE_PIN L1 [get_ports ddr3_dm[0]] +set_property PACKAGE_PIN U1 [get_ports ddr3_dm[1]] +set_property PACKAGE_PIN N2 [get_ports ddr3_dqs_p[0]] +set_property PACKAGE_PIN N1 [get_ports ddr3_dqs_n[0]] +set_property PACKAGE_PIN U2 [get_ports ddr3_dqs_p[1]] +set_property PACKAGE_PIN V2 [get_ports ddr3_dqs_n[1]] +set_property PACKAGE_PIN T8 [get_ports ddr3_addr[13]] +set_property PACKAGE_PIN T6 [get_ports ddr3_addr[12]] +set_property PACKAGE_PIN U6 [get_ports ddr3_addr[11]] +set_property PACKAGE_PIN R6 [get_ports ddr3_addr[10]] +set_property PACKAGE_PIN V7 [get_ports ddr3_addr[9]] +set_property PACKAGE_PIN R8 [get_ports ddr3_addr[8]] +set_property PACKAGE_PIN U7 [get_ports ddr3_addr[7]] +set_property PACKAGE_PIN V6 [get_ports ddr3_addr[6]] +set_property PACKAGE_PIN R7 [get_ports ddr3_addr[5]] +set_property PACKAGE_PIN N6 [get_ports ddr3_addr[4]] +set_property PACKAGE_PIN T1 [get_ports ddr3_addr[3]] +set_property PACKAGE_PIN N4 [get_ports ddr3_addr[2]] +set_property PACKAGE_PIN M6 [get_ports ddr3_addr[1]] +set_property PACKAGE_PIN R2 [get_ports ddr3_addr[0]] +set_property PACKAGE_PIN P2 [get_ports ddr3_ba[2]] +set_property PACKAGE_PIN P4 [get_ports ddr3_ba[1]] +set_property PACKAGE_PIN R1 [get_ports ddr3_ba[0]] +set_property PACKAGE_PIN U9 [get_ports ddr3_ck_p[0]] +set_property PACKAGE_PIN V9 [get_ports ddr3_ck_n[0]] +set_property PACKAGE_PIN P3 [get_ports ddr3_ras_n] +set_property PACKAGE_PIN M4 [get_ports ddr3_cas_n] +set_property PACKAGE_PIN P5 [get_ports ddr3_we_n] +set_property PACKAGE_PIN K6 [get_ports ddr3_reset_n] +set_property PACKAGE_PIN N5 [get_ports ddr3_cke[0]] +set_property PACKAGE_PIN R5 [get_ports ddr3_odt[0]] +set_property PACKAGE_PIN U8 [get_ports ddr3_cs_n[0]] -create_clock -period 40.000 -name VIRTUAL_clk_out3_mmcm -waveform {0.000 20.000} -set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports {GPI[*]}] -set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports {GPI[*]}] -set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCCD] -set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCD] -set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCIn] -set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCIn] -set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCWP] -set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCWP] -set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports UARTSin] -set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports UARTSin] -create_clock -period 12.000 -name VIRTUAL_clk_pll_i -waveform {0.000 6.000} -set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports {GPO[*]}] -set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports {GPO[*]}] -set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCLK] -set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 0.000 [get_ports SDCCLK] -set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCS] -set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCS] -set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCmd] -set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCmd] -set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports UARTSout] -set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports UARTSout] +#create_clock -period 50.000 -name VIRTUAL_clk_out3_mmcm -waveform {0.000 25.000} +#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports {GPI[*]}] +#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports {GPI[*]}] +#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCCD] +#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCD] +#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCIn] +#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCIn] +#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCWP] +#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCWP] +#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports UARTSin] +#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports UARTSin] +#create_clock -period 12.000 -name VIRTUAL_clk_pll_i -waveform {0.000 6.000} +#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports {GPO[*]}] +#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports {GPO[*]}] +#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCLK] +#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 0.000 [get_ports SDCCLK] +#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCS] +#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCS] +#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCmd] +#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCmd] +#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports UARTSout] +#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports UARTSout] #set_output_delay -clock [get_clocks VIRTUAL_clk_pll_i] -min -add_delay 0.000 [get_ports ddr3_reset_n] #set_output_delay -clock [get_clocks VIRTUAL_clk_pll_i] -max -add_delay 80.000 [get_ports ddr3_reset_n]