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Added F_SUPPORTED flag to disable floating point unit when not in MISA

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This commit is contained in:
David Harris 2021-07-05 10:30:46 -04:00
parent ac163e091c
commit 5f91b339aa
3 changed files with 15 additions and 14 deletions
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3
wally-pipelined/regression/wave-dos/peripheral-waves.do
View File

@ -9,7 +9,8 @@ add wave /testbench/clk
add wave /testbench/reset
add wave -divider
add wave /testbench/dut/hart/DataStall
#add wave /testbench/dut/hart/DataStall
add wave /testbench/debug
add wave /testbench/dut/hart/StallF
add wave /testbench/dut/hart/StallD
add wave /testbench/dut/hart/StallE

12
wally-pipelined/src/fpu/fpu.sv
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@ -44,9 +44,8 @@ module fpu (
output logic [`XLEN-1:0] FPUResultW); // FPU result
// *** change FMA to do 16 - 32 - 64 - 128 FEXPBITS
/*generate
if (`F_SUPPORTED) begin */
generate
if (`F_SUPPORTED) begin
// control logic signal instantiation
logic FWriteEnD, FWriteEnE, FWriteEnM, FWriteEnW; // FP register write enable
logic [2:0] FrmD, FrmE, FrmM; // FP rounding mode
@ -401,8 +400,7 @@ module fpu (
//*** put into mem stage
SetFflagsM = FPUFlagsW;
end
/* end else begin
end else begin // no F_SUPPORTED; tie outputs low
assign FStallD = 0;
assign FWriteIntE = 0;
assign FWriteIntM = 0;
@ -410,11 +408,11 @@ module fpu (
assign FWriteDataE = 0;
assign FIntResM = 0;
assign FDivBusyE = 0;
assign IllegalFPUInstrD = 0;
assign IllegalFPUInstrD = 1;
assign SetFflagsM = 0;
assign FPUResultW = 0;
end
endgenerate*/
endgenerate
endmodule // fpu

14
wally-pipelined/testbench/testbench-imperas.sv
View File

@ -515,6 +515,9 @@ string tests32f[] = '{
logic HCLK, HRESETn;
logic [`XLEN-1:0] PCW;
logic [`XLEN-1:0] debug;
assign debug = dut.uncore.dtim.RAM[536872960];
flopenr #(`XLEN) PCWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW);
flopenr #(32) InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW);
@ -656,10 +659,7 @@ string tests32f[] = '{
// Check errors
errors = (i == SIGNATURESIZE+1); // error if file is empty
i = 0;
if (`XLEN == 32)
testadr = (`TIM_BASE+tests[test+1].atohex())/4;
else
testadr = (`TIM_BASE+tests[test+1].atohex())/8;
testadr = (`TIM_BASE+tests[test+1].atohex())/(`XLEN/8);
/* verilator lint_off INFINITELOOP */
while (signature[i] !== 'bx) begin
//$display("signature[%h] = %h", i, signature[i]);
@ -669,14 +669,16 @@ string tests32f[] = '{
// kind of hacky test for garbage right now
errors = errors+1;
$display(" Error on test %s result %d: adr = %h sim = %h, signature = %h",
tests[test], i, (testadr+i)*`XLEN/8, dut.uncore.dtim.RAM[testadr+i], signature[i]);
tests[test], i, (testadr+i)*(`XLEN/8), dut.uncore.dtim.RAM[testadr+i], signature[i]);
$stop;//***debug
end
end
i = i + 1;
end
/* verilator lint_on INFINITELOOP */
if (errors == 0) $display("%s succeeded. Brilliant!!!", tests[test]);
if (errors == 0) begin
$display("%s succeeded. Brilliant!!!", tests[test]);
end
else begin
$display("%s failed with %d errors. :(", tests[test], errors);
totalerrors = totalerrors+1;