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Modified uncore to use AHB bridge to GPIO

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This commit is contained in:
David Harris 2022-07-05 05:02:21 +00:00
parent c8ac05ba7b
commit 5f5ad77d4a
1 changed files with 125 additions and 92 deletions
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217
pipelined/src/uncore/uncore.sv
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@ -81,6 +81,24 @@ module uncore (
logic UARTIntr,GPIOIntr; logic UARTIntr,GPIOIntr;
logic SDCIntM; logic SDCIntM;
logic PCLK, PRESETn, PWRITE, PENABLE;
// logic PSEL, PREADY;
logic [1:0] PSEL, PREADY;
logic [31:0] PADDR;
logic [`XLEN-1:0] PWDATA;
logic [`XLEN/8-1:0] PSTRB;
logic [1:0][`XLEN-1:0] PRDATA;
// logic [`XLEN-1:0][8:0] PRDATA;
logic [`XLEN-1:0] HREADBRIDGE;
logic HRESPBRIDGE, HREADYBRIDGE, HSELBRIDGE, HSELBRIDGED;
// *** to do:
// combinational loop related to HREADY, HREADYOUT through PENABLE
// hook up and test GPIO on AHB
// hook up HWSTRB and remove subword write decoders
// add other peripherals on AHB
// HTRANS encoding
// Determine which region of physical memory (if any) is being accessed // Determine which region of physical memory (if any) is being accessed
// Use a trimmed down portion of the PMA checker - only the address decoders // Use a trimmed down portion of the PMA checker - only the address decoders
// Set access types to all 1 as don't cares because the MMU has already done access checking // Set access types to all 1 as don't cares because the MMU has already done access checking
@ -89,98 +107,109 @@ module uncore (
// unswizzle HSEL signals // unswizzle HSEL signals
assign {HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[7:0]; assign {HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[7:0];
// generate // AHB -> APB bridge
// on-chip RAM ahbapbbridge #(2) ahbapbbridge
if (`RAM_SUPPORTED) begin : ram (.HCLK, .HRESETn, .HSEL({1'b0, HSELGPIO}), .HADDR, .HWDATA, .HWRITE, .HTRANS, .HREADY, .HWSTRB('1),
ram #( .HRDATA(HREADBRIDGE), .HRESP(HRESPBRIDGE), .HREADYOUT(HREADYBRIDGE),
.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram ( .PCLK, .PRESETn, .PSEL, .PWRITE, .PENABLE, .PADDR, .PWDATA, .PSTRB, .PREADY, .PRDATA);
.HCLK, .HRESETn, assign PREADY[1] = 0; // *** replace these with connections to other peripherals
.HSELRam, .HADDR, assign PRDATA[1] = 0;
.HWRITE, .HREADY, .HSIZED, assign HSELBRIDGE = HSELGPIO; // if any of the bridge signals are selected
.HTRANS, .HWDATA, .HREADRam, // This system is showing a combinatonal loop related to HREADY and HREADYBRIDGE and HREADYGPIO
.HRESPRam, .HREADYRam);
end // on-chip RAM
if (`RAM_SUPPORTED) begin : ram
ram #(
.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
.HCLK, .HRESETn,
.HSELRam, .HADDR,
.HWRITE, .HREADY, .HSIZED,
.HTRANS, .HWDATA, .HREADRam,
.HRESPRam, .HREADYRam);
end
if (`BOOTROM_SUPPORTED) begin : bootrom if (`BOOTROM_SUPPORTED) begin : bootrom
ram_orig #(.BASE(`BOOTROM_BASE), .RANGE(`BOOTROM_RANGE)) ram_orig #(.BASE(`BOOTROM_BASE), .RANGE(`BOOTROM_RANGE))
bootrom( bootrom(
.HCLK, .HRESETn, .HCLK, .HRESETn,
.HSELRam(HSELBootRom), .HADDR, .HSELRam(HSELBootRom), .HADDR,
.HWRITE, .HREADY, .HTRANS, .HSIZED, .HWRITE, .HREADY, .HTRANS, .HSIZED,
.HWDATA, .HWDATA,
.HREADRam(HREADBootRom), .HRESPRam(HRESPBootRom), .HREADYRam(HREADYBootRom)); .HREADRam(HREADBootRom), .HRESPRam(HRESPBootRom), .HREADYRam(HREADYBootRom));
end end
// memory-mapped I/O peripherals // memory-mapped I/O peripherals
if (`CLINT_SUPPORTED == 1) begin : clint if (`CLINT_SUPPORTED == 1) begin : clint
clint clint( clint clint(
.HCLK, .HRESETn, .TIMECLK, .HCLK, .HRESETn, .TIMECLK,
.HSELCLINT, .HADDR(HADDR[15:0]), .HWRITE, .HSELCLINT, .HADDR(HADDR[15:0]), .HWRITE,
.HWDATA, .HREADY, .HTRANS, .HSIZED, .HWDATA, .HREADY, .HTRANS, .HSIZED,
.HREADCLINT, .HREADCLINT,
.HRESPCLINT, .HREADYCLINT, .HRESPCLINT, .HREADYCLINT,
.MTIME(MTIME_CLINT), .MTIME(MTIME_CLINT),
.MTimerInt, .MSwInt); .MTimerInt, .MSwInt);
end else begin : clint end else begin : clint
assign MTIME_CLINT = 0; assign MTIME_CLINT = 0;
assign MTimerInt = 0; assign MSwInt = 0; assign MTimerInt = 0; assign MSwInt = 0;
end end
if (`PLIC_SUPPORTED == 1) begin : plic if (`PLIC_SUPPORTED == 1) begin : plic
plic plic( plic plic(
.HCLK, .HRESETn, .HCLK, .HRESETn,
.HSELPLIC, .HADDR(HADDR[27:0]), .HSELPLIC, .HADDR(HADDR[27:0]),
.HWRITE, .HREADY, .HTRANS, .HWDATA, .HWRITE, .HREADY, .HTRANS, .HWDATA,
.UARTIntr, .GPIOIntr, .UARTIntr, .GPIOIntr,
.HREADPLIC, .HRESPPLIC, .HREADYPLIC, .HREADPLIC, .HRESPPLIC, .HREADYPLIC,
.MExtInt, .SExtInt); .MExtInt, .SExtInt);
end else begin : plic end else begin : plic
assign MExtInt = 0; assign MExtInt = 0;
assign SExtInt = 0; assign SExtInt = 0;
end end
if (`GPIO_SUPPORTED == 1) begin : gpio if (`GPIO_SUPPORTED == 1) begin : gpio
gpio gpio( /* gpio gpio(
.HCLK, .HRESETn, .HSELGPIO, .HCLK, .HRESETn, .HSELGPIO,
.HADDR(HADDR[7:0]), .HADDR(HADDR[7:0]),
.HWDATA, .HWDATA,
.HWRITE, .HREADY, .HWRITE, .HREADY,
.HTRANS, .HTRANS,
.HREADGPIO, .HREADGPIO,
.HRESPGPIO, .HREADYGPIO, .HRESPGPIO, .HREADYGPIO,
.GPIOPinsIn, .GPIOPinsIn,
.GPIOPinsOut, .GPIOPinsEn, .GPIOPinsOut, .GPIOPinsEn,
.GPIOIntr); .GPIOIntr); */
gpio_apb gpio(
end else begin : gpio .PCLK, .PRESETn, .PSEL(PSEL[0]), .PADDR(PADDR[7:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE,
assign GPIOPinsOut = 0; assign GPIOPinsEn = 0; assign GPIOIntr = 0; .PRDATA(PRDATA[0]), .PREADY(PREADY[0]),
end .iof0(), .iof1(), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .GPIOIntr);
if (`UART_SUPPORTED == 1) begin : uart end else begin : gpio
uart uart( assign GPIOPinsOut = 0; assign GPIOPinsEn = 0; assign GPIOIntr = 0;
.HCLK, .HRESETn, end
.HSELUART, if (`UART_SUPPORTED == 1) begin : uart
.HADDR(HADDR[2:0]), uart uart(
.HWRITE, .HWDATA, .HCLK, .HRESETn,
.HREADUART, .HRESPUART, .HREADYUART, .HSELUART,
.SIN(UARTSin), .DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1), // from E1A driver from RS232 interface .HADDR(HADDR[2:0]),
.SOUT(UARTSout), .RTSb(), .DTRb(), // to E1A driver to RS232 interface .HWRITE, .HWDATA,
.OUT1b(), .OUT2b(), .INTR(UARTIntr), .TXRDYb(), .RXRDYb()); // to CPU .HREADUART, .HRESPUART, .HREADYUART,
end else begin : uart .SIN(UARTSin), .DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1), // from E1A driver from RS232 interface
assign UARTSout = 0; assign UARTIntr = 0; .SOUT(UARTSout), .RTSb(), .DTRb(), // to E1A driver to RS232 interface
end .OUT1b(), .OUT2b(), .INTR(UARTIntr), .TXRDYb(), .RXRDYb()); // to CPU
if (`SDC_SUPPORTED == 1) begin : sdc end else begin : uart
SDC SDC(.HCLK, .HRESETn, .HSELSDC, .HADDR(HADDR[4:0]), .HWRITE, .HREADY, .HTRANS, assign UARTSout = 0; assign UARTIntr = 0;
.HWDATA, .HREADSDC, .HRESPSDC, .HREADYSDC, end
// sdc interface if (`SDC_SUPPORTED == 1) begin : sdc
.SDCCmdOut, .SDCCmdIn, .SDCCmdOE, .SDCDatIn, .SDCCLK, SDC SDC(.HCLK, .HRESETn, .HSELSDC, .HADDR(HADDR[4:0]), .HWRITE, .HREADY, .HTRANS,
// interrupt to PLIC .HWDATA, .HREADSDC, .HRESPSDC, .HREADYSDC,
.SDCIntM // sdc interface
); .SDCCmdOut, .SDCCmdIn, .SDCCmdOE, .SDCDatIn, .SDCCLK,
end else begin : sdc // interrupt to PLIC
assign SDCCLK = 0; .SDCIntM
assign SDCCmdOut = 0; );
assign SDCCmdOE = 0; end else begin : sdc
end assign SDCCLK = 0;
// endgenerate assign SDCCmdOut = 0;
assign SDCCmdOE = 0;
end
// mux could also include external memory // mux could also include external memory
// AHB Read Multiplexer // AHB Read Multiplexer
@ -188,7 +217,8 @@ module uncore (
({`XLEN{HSELEXTD}} & HRDATAEXT) | ({`XLEN{HSELEXTD}} & HRDATAEXT) |
({`XLEN{HSELCLINTD}} & HREADCLINT) | ({`XLEN{HSELCLINTD}} & HREADCLINT) |
({`XLEN{HSELPLICD}} & HREADPLIC) | ({`XLEN{HSELPLICD}} & HREADPLIC) |
({`XLEN{HSELGPIOD}} & HREADGPIO) | // ({`XLEN{HSELGPIOD}} & HREADGPIO) |
({`XLEN{HSELBRIDGED}} & HREADBRIDGE) |
({`XLEN{HSELBootRomD}} & HREADBootRom) | ({`XLEN{HSELBootRomD}} & HREADBootRom) |
({`XLEN{HSELUARTD}} & HREADUART) | ({`XLEN{HSELUARTD}} & HREADUART) |
({`XLEN{HSELSDCD}} & HREADSDC); ({`XLEN{HSELSDCD}} & HREADSDC);
@ -197,7 +227,8 @@ module uncore (
HSELEXTD & HRESPEXT | HSELEXTD & HRESPEXT |
HSELCLINTD & HRESPCLINT | HSELCLINTD & HRESPCLINT |
HSELPLICD & HRESPPLIC | HSELPLICD & HRESPPLIC |
HSELGPIOD & HRESPGPIO | // HSELGPIOD & HRESPGPIO |
HSELBRIDGE & HRESPBRIDGE |
HSELBootRomD & HRESPBootRom | HSELBootRomD & HRESPBootRom |
HSELUARTD & HRESPUART | HSELUARTD & HRESPUART |
HSELSDC & HRESPSDC; HSELSDC & HRESPSDC;
@ -206,7 +237,8 @@ module uncore (
HSELEXTD & HREADYEXT | HSELEXTD & HREADYEXT |
HSELCLINTD & HREADYCLINT | HSELCLINTD & HREADYCLINT |
HSELPLICD & HREADYPLIC | HSELPLICD & HREADYPLIC |
HSELGPIOD & HREADYGPIO | // HSELGPIOD & HREADYGPIO |
HSELBRIDGED & HREADYBRIDGE |
HSELBootRomD & HREADYBootRom | HSELBootRomD & HREADYBootRom |
HSELUARTD & HREADYUART | HSELUARTD & HREADYUART |
HSELSDCD & HREADYSDC | HSELSDCD & HREADYSDC |
@ -214,5 +246,6 @@ module uncore (
// Address Decoder Delay (figure 4-2 in spec) // Address Decoder Delay (figure 4-2 in spec)
flopr #(9) hseldelayreg(HCLK, ~HRESETn, HSELRegions, {HSELNoneD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD}); flopr #(9) hseldelayreg(HCLK, ~HRESETn, HSELRegions, {HSELNoneD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD});
flopr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HSELBRIDGE, HSELBRIDGED);
endmodule endmodule