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add FP registers to debug scan chain

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Matthew 2024-06-07 23:18:44 -05:00
parent 0d4e0f8b5f
commit 5f5938f3b5
8 changed files with 169 additions and 117 deletions
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32
bin/hw_debug_interface.py
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@ -386,6 +386,38 @@ register_translations = {
"X29" : "0x101D", "X29" : "0x101D",
"X30" : "0x101E", "X30" : "0x101E",
"X31" : "0x101F", "X31" : "0x101F",
"FP0" : "0x1020",
"FP1" : "0x1021",
"FP2" : "0x1022",
"FP3" : "0x1023",
"FP4" : "0x1024",
"FP5" : "0x1025",
"FP6" : "0x1026",
"FP7" : "0x1027",
"FP8" : "0x1028",
"FP9" : "0x1029",
"FP10" : "0x102A",
"FP11" : "0x102B",
"FP12" : "0x102C",
"FP13" : "0x102D",
"FP14" : "0x102E",
"FP15" : "0x102F",
"FP16" : "0x1030",
"FP17" : "0x1031",
"FP18" : "0x1032",
"FP19" : "0x1033",
"FP20" : "0x1034",
"FP21" : "0x1035",
"FP22" : "0x1036",
"FP23" : "0x1037",
"FP24" : "0x1038",
"FP25" : "0x1039",
"FP26" : "0x103A",
"FP27" : "0x103B",
"FP28" : "0x103C",
"FP29" : "0x103D",
"FP30" : "0x103E",
"FP31" : "0x103F",
} }
nonstandard_register_lengths = { nonstandard_register_lengths = {

105
src/debug/dm.sv
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@ -45,15 +45,13 @@ module dm import cvw::*; #(parameter cvw_t P) (
input logic ScanIn, input logic ScanIn,
output logic ScanOut, output logic ScanOut,
output logic GPRSel, output logic GPRSel,
output logic FPRSel,
output logic [4:0] RegAddr,
output logic DebugCapture, output logic DebugCapture,
output logic DebugGPRUpdate, output logic DebugRegUpdate,
output logic [4:0] GPRAddr,
output logic GPRScanEn, output logic GPRScanEn,
input logic GPRScanIn, input logic GPRScanIn,
output logic GPRScanOut, output logic GPRScanOut,
output logic FPRSel,
output logic DebugFPRUpdate,
output logic [4:0] FPRAddr,
output logic FPRScanEn, output logic FPRScanEn,
input logic FPRScanIn, input logic FPRScanIn,
output logic FPRScanOut output logic FPRScanOut
@ -97,21 +95,22 @@ module dm import cvw::*; #(parameter cvw_t P) (
W_ABSTRACTCS, R_ABSTRACTCS, ABST_COMMAND, R_SYSBUSCS, READ_ZERO, W_ABSTRACTCS, R_ABSTRACTCS, ABST_COMMAND, R_SYSBUSCS, READ_ZERO,
INVALID} State; INVALID} State;
enum logic [1:0] {AC_IDLE, AC_GPRUPDATE, AC_SCAN, AC_CAPTURE} AcState, NewAcState; enum logic [1:0] {AC_IDLE, AC_UPDATE, AC_SCAN, AC_CAPTURE} AcState, NewAcState;
// AbsCmd internal state // AbsCmd internal state
logic AcWrite; // Abstract Command write state logic AcWrite; // Abstract Command write state
logic [P.XLEN:0] ScanReg; // The part of the debug scan chain located within DM logic [P.LLEN:0] ScanReg; // The part of the debug scan chain located within DM
logic [P.XLEN-1:0] ScanNext; // New ScanReg value logic [P.LLEN-1:0] ScanNext; // New ScanReg value
logic [P.XLEN-1:0] ARMask; // Masks which bits of the ScanReg get updated logic [P.LLEN-1:0] ARMask; // Masks which bits of the ScanReg get updated
logic [P.XLEN-1:0] PackedDataReg; // Combines DataX msg registers into a single XLEN wide register logic [P.LLEN-1:0] PackedDataReg; // Combines DataX msg registers into a single LLEN wide register
logic [P.XLEN-1:0] MaskedScanReg; // Masks which bits of the ScanReg get written to DataX logic [P.LLEN-1:0] MaskedScanReg; // Masks which bits of the ScanReg get written to DataX
logic [9:0] ShiftCount; // Position of the selected register on the debug scan chain logic [9:0] ShiftCount; // Position of the selected register on the debug scan chain
logic [9:0] ScanChainLen; // Total length of currently selected scan chain logic [9:0] ScanChainLen; // Total length of currently selected scan chain
logic [9:0] Cycle; // DM's current position in the scan chain logic [9:0] Cycle; // DM's current position in the scan chain
logic InvalidRegNo; // Requested RegNo is invalid logic InvalidRegNo; // Requested RegNo is invalid
logic RegReadOnly; // Current RegNo points to a readonly register logic RegReadOnly; // Current RegNo points to a readonly register
logic GPRRegNo; // Requested RegNo is a GPR logic GPRegNo; // Requested RegNo is a GPR
logic FPRegNo; // Requested RegNo is a FPR
logic StoreScanChain; // Store current value of ScanReg into DataX logic StoreScanChain; // Store current value of ScanReg into DataX
logic WriteMsgReg; // Write to DataX logic WriteMsgReg; // Write to DataX
logic WriteScanReg; // Insert data from DataX into ScanReg logic WriteScanReg; // Insert data from DataX into ScanReg
@ -158,7 +157,7 @@ module dm import cvw::*; #(parameter cvw_t P) (
logic Busy; logic Busy;
const logic RelaxedPriv = 1; const logic RelaxedPriv = 1;
logic [2:0] CmdErr; logic [2:0] CmdErr;
const logic [3:0] DataCount = (P.XLEN/32); const logic [3:0] DataCount = (P.LLEN/32);
// Pack registers // Pack registers
assign DMControl = {2'b0, 1'b0, 2'b0, 1'b0, 10'b0, assign DMControl = {2'b0, 1'b0, 2'b0, 1'b0, 10'b0,
@ -214,10 +213,10 @@ module dm import cvw::*; #(parameter cvw_t P) (
case ({ReqOP, ReqAddress}) inside case ({ReqOP, ReqAddress}) inside
{`OP_WRITE,`DATA0} : State <= W_DATA; {`OP_WRITE,`DATA0} : State <= W_DATA;
{`OP_READ,`DATA0} : State <= R_DATA; {`OP_READ,`DATA0} : State <= R_DATA;
{`OP_WRITE,`DATA1} : State <= (P.XLEN >= 64) ? W_DATA : INVALID; {`OP_WRITE,`DATA1} : State <= (P.LLEN >= 64) ? W_DATA : INVALID;
{`OP_READ,`DATA1} : State <= (P.XLEN >= 64) ? R_DATA : INVALID; {`OP_READ,`DATA1} : State <= (P.LLEN >= 64) ? R_DATA : INVALID;
[{`OP_WRITE,`DATA2}:{`OP_WRITE,`DATA3}] : State <= (P.XLEN >= 128) ? W_DATA : INVALID; [{`OP_WRITE,`DATA2}:{`OP_WRITE,`DATA3}] : State <= (P.LLEN >= 128) ? W_DATA : INVALID;
[{`OP_READ,`DATA2}:{`OP_READ,`DATA3}] : State <= (P.XLEN >= 128) ? R_DATA : INVALID; [{`OP_READ,`DATA2}:{`OP_READ,`DATA3}] : State <= (P.LLEN >= 128) ? R_DATA : INVALID;
{`OP_WRITE,`DMCONTROL} : State <= W_DMCONTROL; {`OP_WRITE,`DMCONTROL} : State <= W_DMCONTROL;
{`OP_READ,`DMCONTROL} : State <= R_DMCONTROL; {`OP_READ,`DMCONTROL} : State <= R_DMCONTROL;
{`OP_READ,`DMSTATUS} : State <= DMSTATUS; {`OP_READ,`DMSTATUS} : State <= DMSTATUS;
@ -321,7 +320,7 @@ module dm import cvw::*; #(parameter cvw_t P) (
else begin else begin
case (ReqData[`CMDTYPE]) case (ReqData[`CMDTYPE])
`ACCESS_REGISTER : begin `ACCESS_REGISTER : begin
if (ReqData[`AARSIZE] > $clog2(P.XLEN/8)) // if AARSIZE (encoded) is greater than P.XLEN, set CmdErr, do nothing if (ReqData[`AARSIZE] > $clog2(P.LLEN/8)) // if AARSIZE (encoded) is greater than P.LLEN, set CmdErr, do nothing
CmdErr <= `CMDERR_BUS; CmdErr <= `CMDERR_BUS;
else if (~ReqData[`TRANSFER]); // If not TRANSFER, do nothing else if (~ReqData[`TRANSFER]); // If not TRANSFER, do nothing
else if (InvalidRegNo) else if (InvalidRegNo)
@ -382,13 +381,17 @@ module dm import cvw::*; #(parameter cvw_t P) (
end end
AC_SCAN : begin AC_SCAN : begin
if (Cycle == ScanChainLen) if ((GPRegNo | FPRegNo) & AcWrite & (Cycle == ScanChainLen)) // Writes to GPR/FPR are shifted in len(GPR) or len(FPR) cycles
AcState <= (GPRRegNo & AcWrite) ? AC_GPRUPDATE : AC_IDLE; AcState <= AC_UPDATE;
else if ((GPRegNo | FPRegNo) & ~AcWrite & (Cycle == P.LLEN)) // Reads from GPR/FPR are shifted in len(ScanReg) cycles
AcState <= AC_IDLE;
else if (~(GPRegNo | FPRegNo) & (Cycle == ScanChainLen)) // Misc scanchain must be scanned completely
AcState <= AC_IDLE;
else else
Cycle <= Cycle + 1; Cycle <= Cycle + 1;
end end
AC_GPRUPDATE : begin AC_UPDATE : begin
AcState <= AC_IDLE; AcState <= AC_IDLE;
end end
endcase endcase
@ -397,50 +400,68 @@ module dm import cvw::*; #(parameter cvw_t P) (
assign Busy = ~(AcState == AC_IDLE); assign Busy = ~(AcState == AC_IDLE);
assign DebugCapture = (AcState == AC_CAPTURE); assign DebugCapture = (AcState == AC_CAPTURE);
assign DebugGPRUpdate = (AcState == AC_GPRUPDATE); assign DebugRegUpdate = (AcState == AC_UPDATE);
// Scan Chain // Scan Chain
assign GPRSel = GPRRegNo & (AcState != AC_IDLE); assign GPRSel = GPRegNo & (AcState != AC_IDLE);
assign ScanReg[P.XLEN] = GPRSel ? GPRScanIn : ScanIn; assign FPRSel = FPRegNo & (AcState != AC_IDLE);
assign ScanOut = GPRSel ? 1'b0 : ScanReg[0];
assign GPRScanOut = GPRSel ? ScanReg[0] : 1'b0;
assign ScanEn = ~GPRSel & (AcState == AC_SCAN);
assign GPRScanEn = GPRSel & (AcState == AC_SCAN);
// Load data from message registers into scan chain always_comb begin
if (P.XLEN == 32) {ScanOut,GPRScanOut,FPRScanOut} = 0;
{ScanEn,GPRScanEn,FPRScanEn} = 0;
case ({GPRSel, FPRSel})
2'b10 : begin
ScanReg[P.LLEN] = GPRScanIn;
GPRScanOut = ScanReg[0];
GPRScanEn = (AcState == AC_SCAN);
end
2'b01 : begin
ScanReg[P.LLEN] = FPRScanIn;
FPRScanOut = ScanReg[0];
FPRScanEn = (AcState == AC_SCAN);
end
2'b00 : begin
ScanReg[P.LLEN] = ScanIn;
ScanOut = ScanReg[0];
ScanEn = (AcState == AC_SCAN);
end
endcase
end
if (P.LLEN == 32)
assign PackedDataReg = Data0; assign PackedDataReg = Data0;
else if (P.XLEN == 64) else if (P.LLEN == 64)
assign PackedDataReg = {Data1,Data0}; assign PackedDataReg = {Data1,Data0};
else if (P.XLEN == 128) else if (P.LLEN == 128)
assign PackedDataReg = {Data3,Data2,Data1,Data0}; assign PackedDataReg = {Data3,Data2,Data1,Data0};
assign WriteScanReg = AcWrite & (~GPRRegNo & (Cycle == ShiftCount) | GPRRegNo & (Cycle == 0)); // Load data from message registers into scan chain
assign WriteScanReg = AcWrite & (~(GPRegNo | FPRegNo) & (Cycle == ShiftCount) | (GPRegNo | FPRegNo) & (Cycle == 0));
genvar i; genvar i;
for (i=0; i<P.XLEN; i=i+1) begin for (i=0; i<P.LLEN; i=i+1) begin
// ARMask is used as write enable for subword overwrites (basic mask would overwrite neighbors in the chain) // ARMask is used as write enable for subword overwrites (basic mask would overwrite neighbors in the chain)
assign ScanNext[i] = WriteScanReg & ARMask[i] ? PackedDataReg[i] : ScanReg[i+1]; assign ScanNext[i] = WriteScanReg & ARMask[i] ? PackedDataReg[i] : ScanReg[i+1];
flopenr #(1) scanreg (.clk, .reset(rst), .en(AcState == AC_SCAN), .d(ScanNext[i]), .q(ScanReg[i])); flopenr #(1) scanreg (.clk, .reset(rst), .en(AcState == AC_SCAN), .d(ScanNext[i]), .q(ScanReg[i]));
end end
// Message Registers // Message Registers
assign MaskedScanReg = ARMask & ScanReg[P.XLEN:1]; assign MaskedScanReg = ARMask & ScanReg[P.LLEN:1];
assign WriteMsgReg = (State == W_DATA) & ~Busy; assign WriteMsgReg = (State == W_DATA) & ~Busy;
assign StoreScanChain = (AcState == AC_SCAN) & (Cycle == ShiftCount) & ~AcWrite; assign StoreScanChain = (AcState == AC_SCAN) & (Cycle == ShiftCount) & ~AcWrite;
assign Data0Wr = StoreScanChain ? MaskedScanReg[31:0] : ReqData;; assign Data0Wr = WriteMsgReg ? ReqData : MaskedScanReg[31:0];
flopenr #(32) data0reg (.clk, .reset(rst), .en(StoreScanChain | WriteMsgReg & (ReqAddress == `DATA0)), .d(Data0Wr), .q(Data0)); flopenr #(32) data0reg (.clk, .reset(rst), .en(StoreScanChain | WriteMsgReg & (ReqAddress == `DATA0)), .d(Data0Wr), .q(Data0));
if (P.XLEN >= 64) begin if (P.LLEN >= 64) begin
assign Data1Wr = StoreScanChain ? MaskedScanReg[63:32] : ReqData; assign Data1Wr = WriteMsgReg ? ReqData : MaskedScanReg[63:32];
flopenr #(32) data1reg (.clk, .reset(rst), .en(StoreScanChain | WriteMsgReg & (ReqAddress == `DATA1)), .d(Data1Wr), .q(Data1)); flopenr #(32) data1reg (.clk, .reset(rst), .en(StoreScanChain | WriteMsgReg & (ReqAddress == `DATA1)), .d(Data1Wr), .q(Data1));
end end
if (P.XLEN == 128) begin if (P.LLEN == 128) begin
assign Data2Wr = StoreScanChain ? MaskedScanReg[95:64] : ReqData; assign Data2Wr = WriteMsgReg ? ReqData : MaskedScanReg[95:64];
assign Data3Wr = StoreScanChain ? MaskedScanReg[127:96] : ReqData; assign Data3Wr = WriteMsgReg ? ReqData : MaskedScanReg[127:96];
flopenr #(32) data2reg (.clk, .reset(rst), .en(StoreScanChain | WriteMsgReg & (ReqAddress == `DATA2)), .d(Data2Wr), .q(Data2)); flopenr #(32) data2reg (.clk, .reset(rst), .en(StoreScanChain | WriteMsgReg & (ReqAddress == `DATA2)), .d(Data2Wr), .q(Data2));
flopenr #(32) data3reg (.clk, .reset(rst), .en(StoreScanChain | WriteMsgReg & (ReqAddress == `DATA3)), .d(Data3Wr), .q(Data3)); flopenr #(32) data3reg (.clk, .reset(rst), .en(StoreScanChain | WriteMsgReg & (ReqAddress == `DATA3)), .d(Data3Wr), .q(Data3));
end end
rad #(P) regnodecode(.AarSize(ReqData[`AARSIZE]),.Regno(ReqData[`REGNO]),.GPRRegNo,.ScanChainLen,.ShiftCount,.InvalidRegNo,.RegReadOnly,.GPRAddr,.ARMask); rad #(P) regnodecode(.AarSize(ReqData[`AARSIZE]),.Regno(ReqData[`REGNO]),.GPRegNo,.FPRegNo,.ScanChainLen,.ShiftCount,.InvalidRegNo,.RegReadOnly,.RegAddr,.ARMask);
endmodule endmodule

55
src/debug/rad.sv
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@ -28,13 +28,14 @@
module rad import cvw::*; #(parameter cvw_t P) ( module rad import cvw::*; #(parameter cvw_t P) (
input logic [2:0] AarSize, input logic [2:0] AarSize,
input logic [15:0] Regno, input logic [15:0] Regno,
output logic GPRRegNo, output logic GPRegNo,
output logic FPRegNo,
output logic [9:0] ScanChainLen, output logic [9:0] ScanChainLen,
output logic [9:0] ShiftCount, output logic [9:0] ShiftCount,
output logic InvalidRegNo, output logic InvalidRegNo,
output logic RegReadOnly, output logic RegReadOnly,
output logic [4:0] GPRAddr, output logic [4:0] RegAddr,
output logic [P.XLEN-1:0] ARMask output logic [P.LLEN-1:0] ARMask
); );
`include "debug.vh" `include "debug.vh"
@ -52,6 +53,7 @@ module rad import cvw::*; #(parameter cvw_t P) (
+ MEMRWMLEN + INSTRVALIDMLEN + WRITEDATAMLEN + MEMRWMLEN + INSTRVALIDMLEN + WRITEDATAMLEN
+ IEUADRMLEN + READDATAMLEN; + IEUADRMLEN + READDATAMLEN;
localparam GPRCHAINLEN = P.XLEN; localparam GPRCHAINLEN = P.XLEN;
localparam FPRCHAINLEN = P.FLEN;
localparam MISA_IDX = MISALEN; localparam MISA_IDX = MISALEN;
localparam TRAPM_IDX = MISA_IDX + TRAPMLEN; localparam TRAPM_IDX = MISA_IDX + TRAPMLEN;
@ -63,29 +65,31 @@ module rad import cvw::*; #(parameter cvw_t P) (
localparam IEUADRM_IDX = WRITEDATAM_IDX + IEUADRMLEN; localparam IEUADRM_IDX = WRITEDATAM_IDX + IEUADRMLEN;
localparam READDATAM_IDX = IEUADRM_IDX + READDATAMLEN; localparam READDATAM_IDX = IEUADRM_IDX + READDATAMLEN;
logic [P.XLEN:0] Mask; logic [P.LLEN:0] Mask;
assign ScanChainLen = GPRRegNo ? GPRCHAINLEN : SCANCHAINLEN; assign RegAddr = Regno[4:0];
assign ScanChainLen = GPRegNo ? GPRCHAINLEN : FPRegNo ? FPRCHAINLEN : SCANCHAINLEN;
if (P.E_SUPPORTED)
assign GPRAddr = Regno[3:0];
else
assign GPRAddr = Regno[4:0];
// Register decoder // Register decoder
always_comb begin always_comb begin
InvalidRegNo = 0; InvalidRegNo = 0;
RegReadOnly = 0; RegReadOnly = 0;
GPRRegNo = 0; GPRegNo = 0;
casez (Regno) FPRegNo = 0;
16'h100? : begin case (Regno) inside
[`X0_REGNO:`X15_REGNO] : begin
ShiftCount = P.XLEN - 1; ShiftCount = P.XLEN - 1;
GPRRegNo = 1; GPRegNo = 1;
end end
16'h101? : begin [`X16_REGNO:`X31_REGNO] : begin
ShiftCount = P.XLEN - 1; ShiftCount = P.XLEN - 1;
InvalidRegNo = P.E_SUPPORTED; InvalidRegNo = P.E_SUPPORTED;
GPRRegNo = 1; GPRegNo = 1;
end
[`FP0_REGNO:`FP31_REGNO] : begin
ShiftCount = P.FLEN - 1;
InvalidRegNo = ~(P.F_SUPPORTED | P.D_SUPPORTED | P.Q_SUPPORTED);
FPRegNo = 1;
end end
`MISA_REGNO : begin `MISA_REGNO : begin
ShiftCount = SCANCHAINLEN - MISA_IDX; ShiftCount = SCANCHAINLEN - MISA_IDX;
@ -123,20 +127,21 @@ module rad import cvw::*; #(parameter cvw_t P) (
// Mask calculator // Mask calculator
always_comb begin always_comb begin
Mask = 0; Mask = 0;
case(Regno) case (Regno) inside
`TRAPM_REGNO : Mask = {1{1'b1}}; `TRAPM_REGNO : Mask = {1{1'b1}};
`INSTRM_REGNO : Mask = {32{1'b1}}; `INSTRM_REGNO : Mask = {32{1'b1}};
`MEMRWM_REGNO : Mask = {2{1'b1}}; `MEMRWM_REGNO : Mask = {2{1'b1}};
`INSTRVALIDM_REGNO : Mask = {1{1'b1}}; `INSTRVALIDM_REGNO : Mask = {1{1'b1}};
`READDATAM_REGNO : Mask = {P.LLEN{1'b1}}; `READDATAM_REGNO : Mask = {P.LLEN{1'b1}};
default : Mask = {P.XLEN{1'b1}}; [`FP0_REGNO:`FP31_REGNO] : Mask = {P.FLEN{1'b1}};
default : Mask = {P.XLEN{1'b1}};
endcase endcase
end end
assign ARMask[31:0] = Mask[31:0]; assign ARMask[31:0] = Mask[31:0];
if (P.XLEN >= 64) if (P.LLEN >= 64)
assign ARMask[63:32] = (AarSize == 3'b011 | AarSize == 3'b100) ? Mask[63:32] : '0; assign ARMask[63:32] = (AarSize == 3'b011 | AarSize == 3'b100) ? Mask[63:32] : '0;
if (P.XLEN == 128) if (P.LLEN == 128)
assign ARMask[127:64] = (AarSize == 3'b100) ? Mask[127:64] : '0; assign ARMask[127:64] = (AarSize == 3'b100) ? Mask[127:64] : '0;
endmodule endmodule

29
src/fpu/fpu.sv
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@ -61,15 +61,12 @@ module fpu import cvw::*; #(parameter cvw_t P) (
input logic [P.FLEN-1:0] ReadDataW, // Read data (from LSU) input logic [P.FLEN-1:0] ReadDataW, // Read data (from LSU)
output logic [P.XLEN-1:0] FCvtIntResW, // convert result to to be written to integer register (to IEU) output logic [P.XLEN-1:0] FCvtIntResW, // convert result to to be written to integer register (to IEU)
output logic FCvtIntW, // select FCvtIntRes (to IEU) output logic FCvtIntW, // select FCvtIntRes (to IEU)
output logic [P.XLEN-1:0] FIntDivResultW // Result from integer division (to IEU) output logic [P.XLEN-1:0] FIntDivResultW, // Result from integer division (to IEU)
// Debug scan chain // Debug scan chain
input logic DebugScanEn,
input logic DebugScanIn,
output logic DebugScanOut,
input logic FPRSel, input logic FPRSel,
input logic DebugCapture, input logic DebugCapture,
input logic DebugFPRUpdate, input logic DebugRegUpdate,
input logic [4:0] FPRAddr, input logic [4:0] RegAddr,
input logic FPRScanEn, input logic FPRScanEn,
input logic FPRScanIn, input logic FPRScanIn,
output logic FPRScanOut output logic FPRScanOut
@ -181,7 +178,11 @@ module fpu import cvw::*; #(parameter cvw_t P) (
logic FRoundNVE, FRoundNXE; // Zfa fround invalid and inexact flags logic FRoundNVE, FRoundNXE; // Zfa fround invalid and inexact flags
// Debug signals // Debug signals
logic [P.XLEN-1:0] DebugFPRWriteD; logic FRegWriteWM;
logic [4:0] RA1;
logic [4:0] WA1;
logic [P.FLEN-1:0] FResultWM;
logic [P.FLEN-1:0] DebugFPRWriteD;
////////////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////////////
// Decode Stage: fctrl decoder, read register file // Decode Stage: fctrl decoder, read register file
@ -201,14 +202,14 @@ module fpu import cvw::*; #(parameter cvw_t P) (
// Access FPRs from Debug Module // Access FPRs from Debug Module
if (P.DEBUG_SUPPORTED) begin if (P.DEBUG_SUPPORTED) begin
fregfile #(P.FLEN) fregfile (.clk, .reset, .we4(FRegWriteWM), fregfile #(P.FLEN) fregfile (.clk, .reset, .we4(FRegWriteWM),
.a1(Rs1DM), .a2(InstrD[24:20]), .a3(InstrD[31:27]), .a1(RA1), .a2(InstrD[24:20]), .a3(InstrD[31:27]),
.a4(RdWM), .wd4(FResultWM), .a4(WA1), .wd4(FResultWM),
.rd1(FRD1D), .rd2(FRD2D), .rd3(FRD3D)); .rd1(FRD1D), .rd2(FRD2D), .rd3(FRD3D));
assign FRegWriteWM = FPRSel ? DebugFPRUpdate : FRegWriteW; assign FRegWriteWM = FPRSel ? DebugRegUpdate : FRegWriteW;
assign Rs1DM = FPRSel ? FPRAddr : InstrD[19:15]; assign RA1 = FPRSel ? RegAddr : InstrD[19:15];
assign RdWM = FPRSel ? FPRAddr : RdW; assign WA1 = FPRSel ? RegAddr : RdW;
assign FResultWM = GPRSel ? DebugFPRWriteD : FResultW; assign FResultWM = FPRSel ? DebugFPRWriteD : FResultW;
flopenrs #(P.XLEN) GPRScanReg(.clk, .reset, .en(DebugCapture), .d(FRD1D), .q(DebugFPRWriteD), .scan(FPRScanEn), .scanin(FPRScanIn), .scanout(FPRScanOut)); flopenrs #(P.FLEN) FPScanReg(.clk, .reset, .en(DebugCapture), .d(FRD1D), .q(DebugFPRWriteD), .scan(FPRScanEn), .scanin(FPRScanIn), .scanout(FPRScanOut));
end else begin end else begin
fregfile #(P.FLEN) fregfile (.clk, .reset, .we4(FRegWriteW), fregfile #(P.FLEN) fregfile (.clk, .reset, .we4(FRegWriteW),
.a1(InstrD[19:15]), .a2(InstrD[24:20]), .a3(InstrD[31:27]), .a1(InstrD[19:15]), .a2(InstrD[24:20]), .a3(InstrD[31:27]),

12
src/ieu/datapath.sv
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@ -80,8 +80,8 @@ module datapath import cvw::*; #(parameter cvw_t P) (
output logic DebugScanOut, output logic DebugScanOut,
input logic GPRSel, input logic GPRSel,
input logic DebugCapture, input logic DebugCapture,
input logic DebugGPRUpdate, input logic DebugRegUpdate,
input logic [4:0] GPRAddr, input logic [4:0] RegAddr,
input logic GPRScanEn, input logic GPRScanEn,
input logic GPRScanIn, input logic GPRScanIn,
output logic GPRScanOut output logic GPRScanOut
@ -119,11 +119,11 @@ module datapath import cvw::*; #(parameter cvw_t P) (
// Access GPRs from Debug Module // Access GPRs from Debug Module
if (P.DEBUG_SUPPORTED) begin if (P.DEBUG_SUPPORTED) begin
regfile #(P.XLEN, P.E_SUPPORTED) regf(clk, reset, RegWriteWM, Rs1DM, Rs2D, RdWM, ResultWM, R1D, R2D); regfile #(P.XLEN, P.E_SUPPORTED) regf(clk, reset, RegWriteWM, Rs1DM, Rs2D, RdWM, ResultWM, R1D, R2D);
assign RegWriteWM = GPRSel ? DebugGPRUpdate : RegWriteW; assign RegWriteWM = GPRSel ? DebugRegUpdate : RegWriteW;
assign Rs1DM = GPRSel ? GPRAddr : Rs1D; assign Rs1DM = GPRSel ? RegAddr : Rs1D;
assign RdWM = GPRSel ? GPRAddr : RdW; assign RdWM = GPRSel ? RegAddr : RdW;
assign ResultWM = GPRSel ? DebugGPRWriteD : ResultW; assign ResultWM = GPRSel ? DebugGPRWriteD : ResultW;
flopenrs #(P.XLEN) GPRScanReg(.clk, .reset, .en(DebugCapture), .d(R1D), .q(DebugGPRWriteD), .scan(GPRScanEn), .scanin(GPRScanIn), .scanout(GPRScanOut)); flopenrs #(P.XLEN) GPScanReg(.clk, .reset, .en(DebugCapture), .d(R1D), .q(DebugGPRWriteD), .scan(GPRScanEn), .scanin(GPRScanIn), .scanout(GPRScanOut));
end else begin end else begin
regfile #(P.XLEN, P.E_SUPPORTED) regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, R1D, R2D); regfile #(P.XLEN, P.E_SUPPORTED) regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, R1D, R2D);
end end

6
src/ieu/ieu.sv
View File

@ -86,8 +86,8 @@ module ieu import cvw::*; #(parameter cvw_t P) (
// GPR debug scan chain // GPR debug scan chain
input logic GPRSel, input logic GPRSel,
input logic DebugCapture, input logic DebugCapture,
input logic DebugGPRUpdate, input logic DebugRegUpdate,
input logic [4:0] GPRAddr, input logic [4:0] RegAddr,
input logic GPRScanEn, input logic GPRScanEn,
input logic GPRScanIn, input logic GPRScanIn,
output logic GPRScanOut output logic GPRScanOut
@ -143,5 +143,5 @@ module ieu import cvw::*; #(parameter cvw_t P) (
.StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW, .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW,
.StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW, .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW,
.CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .DebugScanEn, .DebugScanIn(DSCR), .DebugScanOut, .CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .DebugScanEn, .DebugScanIn(DSCR), .DebugScanOut,
.GPRSel, .DebugCapture, .DebugGPRUpdate, .GPRAddr, .GPRScanEn, .GPRScanIn, .GPRScanOut); .GPRSel, .DebugCapture, .DebugRegUpdate, .RegAddr, .GPRScanEn, .GPRScanIn, .GPRScanOut);
endmodule endmodule

15
src/wally/wallypipelinedcore.sv
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@ -52,14 +52,12 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
output logic DebugScanOut, output logic DebugScanOut,
input logic GPRSel, input logic GPRSel,
input logic DebugCapture, input logic DebugCapture,
input logic DebugGPRUpdate, input logic DebugRegUpdate,
input logic [4:0] GPRAddr, input logic [4:0] RegAddr,
input logic GPRScanEn, input logic GPRScanEn,
input logic GPRScanIn, input logic GPRScanIn,
output logic GPRScanOut, output logic GPRScanOut,
input logic FPRSel, input logic FPRSel,
input logic DebugFPRUpdate,
input logic [4:0] FPRAddr,
input logic FPRScanEn, input logic FPRScanEn,
input logic FPRScanIn, input logic FPRScanIn,
output logic FPRScanOut output logic FPRScanOut
@ -238,7 +236,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
.StructuralStallD, .LoadStallD, .StoreStallD, .PCSrcE, .StructuralStallD, .LoadStallD, .StoreStallD, .PCSrcE,
.CSRReadM, .CSRWriteM, .PrivilegedM, .CSRWriteFenceM, .InvalidateICacheM, .CSRReadM, .CSRWriteM, .PrivilegedM, .CSRWriteFenceM, .InvalidateICacheM,
.DebugScanEn, .DebugScanIn(ScanReg[2]), .DebugScanOut(ScanReg[3]), .DebugScanEn, .DebugScanIn(ScanReg[2]), .DebugScanOut(ScanReg[3]),
.GPRSel, .DebugCapture, .DebugGPRUpdate, .GPRAddr, .GPRScanEn, .GPRScanIn, .GPRScanOut); .GPRSel, .DebugCapture, .DebugRegUpdate, .RegAddr, .GPRScanEn, .GPRScanIn, .GPRScanOut);
lsu #(P) lsu( lsu #(P) lsu(
.clk, .reset, .StallM, .FlushM, .StallW, .FlushW, .clk, .reset, .StallM, .FlushM, .StallW, .FlushW,
@ -379,13 +377,10 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
.IllegalFPUInstrD, // Is the instruction an illegal fpu instruction .IllegalFPUInstrD, // Is the instruction an illegal fpu instruction
.SetFflagsM, // FPU flags (to privileged unit) .SetFflagsM, // FPU flags (to privileged unit)
.FIntDivResultW, .FIntDivResultW,
.DebugScanEn,
.DebugScanIn(ScanReg[2]),
.DebugScanOut(ScanReg[3]),
.FPRSel, .FPRSel,
.DebugCapture, .DebugCapture,
.DebugFPRUpdate, .DebugRegUpdate,
.FPRAddr, .RegAddr,
.FPRScanEn, .FPRScanEn,
.FPRScanIn, .FPRScanIn,
.FPRScanOut); .FPRScanOut);

20
src/wally/wallypipelinedsoc.sv
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@ -81,14 +81,12 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) (
logic ScanOut; logic ScanOut;
logic GPRSel; logic GPRSel;
logic DebugCapture; logic DebugCapture;
logic DebugGPRUpdate; logic DebugRegUpdate;
logic [4:0] GPRAddr; logic [4:0] RegAddr;
logic GPRScanEn; logic GPRScanEn;
logic GPRScanIn; logic GPRScanIn;
logic GPRScanOut; logic GPRScanOut;
logic FPRSel; logic FPRSel;
logic DebugFPRUpdate;
logic [4:0] FPRAddr;
logic FPRScanEn; logic FPRScanEn;
logic FPRScanIn; logic FPRScanIn;
logic FPRScanOut; logic FPRScanOut;
@ -102,8 +100,8 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) (
.HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB,
.HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK,
.DebugStall, .DebugScanEn(ScanEn), .DebugScanIn(ScanOut), .DebugScanOut(ScanIn), .DebugStall, .DebugScanEn(ScanEn), .DebugScanIn(ScanOut), .DebugScanOut(ScanIn),
.GPRSel, .DebugCapture, .DebugGPRUpdate, .GPRAddr, .GPRScanEn, .GPRScanIn(GPRScanOut), .GPRScanOut(GPRScanIn), .GPRSel, .DebugCapture, .DebugRegUpdate, .RegAddr, .GPRScanEn, .GPRScanIn(GPRScanOut), .GPRScanOut(GPRScanIn),
.FPRSel, .DebugFPRUpdate, .FPRAddr, .FPRScanEn, .FPRScanIn, .FPRScanOut); .FPRSel, .FPRScanEn, .FPRScanIn(FPRScanOut), .FPRScanOut(FPRScanIn));
// instantiate uncore if a bus interface exists // instantiate uncore if a bus interface exists
if (P.BUS_SUPPORTED) begin : uncoregen // Hack to work around Verilator bug https://github.com/verilator/verilator/issues/4769 if (P.BUS_SUPPORTED) begin : uncoregen // Hack to work around Verilator bug https://github.com/verilator/verilator/issues/4769
@ -120,12 +118,12 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) (
// instantiate debug module // instantiate debug module
if (P.DEBUG_SUPPORTED) begin : dm if (P.DEBUG_SUPPORTED) begin : dm
dm #(P) dm (.clk, .rst(reset), .NdmReset, .tck, .tdi, .tms, .tdo, dm #(P) dm (.clk, .rst(reset), .NdmReset, .tck, .tdi, .tms, .tdo,
.DebugStall, .ScanEn, .ScanIn, .ScanOut, .GPRSel, .DebugCapture, .DebugGPRUpdate, .DebugStall, .ScanEn, .ScanIn, .ScanOut, .GPRSel, .DebugCapture, .DebugRegUpdate,
.GPRAddr, .GPRScanEn, .GPRScanIn, .GPRScanOut, .FPRSel, .DebugFPRUpdate, .RegAddr, .GPRScanEn, .GPRScanIn, .GPRScanOut, .FPRSel,
.FPRAddr, .FPRScanEn, .FPRScanIn, .FPRScanOut); .FPRScanEn, .FPRScanIn, .FPRScanOut);
end else begin end else begin
assign {NdmReset, DebugStall, ScanOut, GPRSel, DebugCapture, DebugGPRUpdate, GPRAddr, GPRScanEn, GPRScanOut, assign {NdmReset, DebugStall, ScanOut, GPRSel, DebugCapture, DebugRegUpdate, RegAddr, GPRScanEn, GPRScanOut,
FPRSel, DebugFPRUpdate, FPRAddr, FPRScanEn, FPRScanOut} = '0; FPRSel, FPRScanEn, FPRScanOut} = '0;
end end
endmodule endmodule