diff --git a/site-setup.sh b/site-setup.sh
index de10a758e..80e9acbbe 100755
--- a/site-setup.sh
+++ b/site-setup.sh
@@ -13,13 +13,23 @@ export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu                   # Change thi
 export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu                # Change this to your Synopsys license server
 export IMPERASD_LICENSE_FILE=27020@zircon.eng.hmc.edu               # Change this to your Imperas license server
 export QUESTA_HOME=/cad/mentor/questa_sim-2023.4/questasim          # Change this for your path to Questa, excluding bin
-export DC_HOME=/cad/synopsys/SYN                                    # Change this for your path to Synopsys Design Compiler, excluding bin
+export DC_HOME=/cad/synopsys/SYN                                    # Change this for your path to Synopsys DC, excluding bin
 export VCS_HOME=/cad/synopsys/vcs/U-2023.03-SP2-4                   # Change this for your path to Synopsys VCS, excluding bin
 
 # Tools
 # Questa and Synopsys
 export PATH=$QUESTA_HOME/bin:$DC_HOME/bin:$VCS_HOME/bin:$PATH
 
+# Environmental variables for SoC
+export SYN_pdk=/proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/
+#export osupdk=/import/yukari1/pdk/TSMC/28/CMOS/HPC+/stclib/9-track/tcbn28hpcplusbwp30p140-set/tcbn28hpcplusbwp30p140_190a_FE/
+export SYN_TLU=/home/jstine/TLU+
+#export OSUTLU=/import/yukari1/pdk/TSMC/TLU+
+export SYN_MW=/home/jstine/MW
+#export OSUMW=/import/yukari1/pdk/TSMC/MW
+export SYN_memory=/home/jstine/WallyMem/rv64gc/
+#export osumemory=/import/yukari1/pdk/TSMC/WallyMem/rv64gc/
+
 # GCC
 if [ -z "$LD_LIBRARY_PATH" ]; then
     export LD_LIBRARY_PATH=$RISCV/riscv64-unknown-elf/lib
diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup
index e4de11db6..0211ce51e 100755
--- a/synthDC/.synopsys_dc.setup
+++ b/synthDC/.synopsys_dc.setup
@@ -18,24 +18,16 @@ if {$tech == "sky130"} {
     set s9lib $timing_lib/sky90/sky90_sc/V1.7.4/lib
     lappend search_path $s9lib
 } elseif {$tech == "tsmc28"} {
-    set pdk /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/
-    set osupdk /import/yukari1/pdk/TSMC/28/CMOS/HPC+/stclib/9-track/tcbn28hpcplusbwp30p140-set/tcbn28hpcplusbwp30p140_190a_FE/
-    set s10lib $pdk/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a
+    set s10lib $SYN_pdk/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a
     lappend search_path $s10lib
 } elseif {$tech == "tsmc28psyn"} {
-    set TLU /home/jstine/TLU+
-    set OSUTLU /import/yukari1/pdk/TSMC/TLU+    
-    set pdk /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/
-    set osupdk /import/yukari1/pdk/TSMC/28/CMOS/HPC+/stclib/9-track/tcbn28hpcplusbwp30p140-set/tcbn28hpcplusbwp30p140_190a_FE/    
-    set s10lib $pdk/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a
+    set s10lib $SYN_pdk/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a
     lappend search_path $s10lib
     set TLUPLUS true
     set mw_logic1_net VDD
     set mw_logic0_net VSS
-    set CAPTABLE $TLU/1p8m/
-    set MW /home/jstine/MW
-    set OSUMW /import/yukari1/pdk/TSMC/MW
-    set MW_REFERENCE_LIBRARY $MW
+    set CAPTABLE $SYN_TLU/1p8m/
+    set MW_REFERENCE_LIBRARY $SYN_MW
     set MW_TECH_FILE tcbn28hpcplusbwp30p140
     set MIN_TLU_FILE $CAPTABLE/crn28hpc+_1p08m+ut-alrdl_5x1z1u_rcbest.tluplus
     set MAX_TLU_FILE $CAPTABLE/crn28hpc+_1p08m+ut-alrdl_5x1z1u_rcworst.tluplus
@@ -70,12 +62,10 @@ lappend search_path ./scripts
 lappend search_path ./hdl
 lappend search_path ./mapped
 if {($tech == "tsmc28psyn")} {
-    set memory /home/jstine/WallyMem/rv64gc/
-    set osumemory /import/yukari1/pdk/TSMC/WallyMem/rv64gc/    
-    lappend target_library $memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db
-    lappend target_library $memory/ts1n28hpcpsvtb64x44m4sw_180a/NLDM/ts1n28hpcpsvtb64x44m4sw_tt0p9v25c.db
-    lappend target_library $memory/tsdn28hpcpa1024x68m4mw_130a/NLDM/tsdn28hpcpa1024x68m4mw_tt0p9v25c.db
-    lappend target_library $memory/tsdn28hpcpa64x32m4mw_130a/NLDM/tsdn28hpcpa64x32m4mw_tt0p9v25c.db
+    lappend target_library $SYN_memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db
+    lappend target_library $SYN_memory/ts1n28hpcpsvtb64x44m4sw_180a/NLDM/ts1n28hpcpsvtb64x44m4sw_tt0p9v25c.db
+    lappend target_library $SYN_memory/tsdn28hpcpa1024x68m4mw_130a/NLDM/tsdn28hpcpa1024x68m4mw_tt0p9v25c.db
+    lappend target_library $SYN_memory/tsdn28hpcpa64x32m4mw_130a/NLDM/tsdn28hpcpa64x32m4mw_tt0p9v25c.db
     lappend mw_reference_library $MW_REFERENCE_LIBRARY/ts1n28hpcpsvtb64x44m4sw
     lappend mw_reference_library $MW_REFERENCE_LIBRARY/ts1n28hpcpsvtb64x128m4sw
     lappend mw_reference_library $MW_REFERENCE_LIBRARY/tsdn28hpcpa1024x68m4mw
@@ -86,8 +76,8 @@ if {($tech == "tsmc28psyn")} {
 set link_library "$target_library $synthetic_library"
 
 # Set up User Information
-set company "Oklahoma State University"
-set user    "James E. Stine"
+set company "Detect-o-rama"
+set user    "Ben Bitdiddle"
 
 # Alias
 alias ra report_area