diff --git a/pipelined/src/lsu/buscachefsm.sv b/pipelined/src/cache/buscachefsm.sv
similarity index 100%
rename from pipelined/src/lsu/buscachefsm.sv
rename to pipelined/src/cache/buscachefsm.sv
diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/cache/cachedp.sv
similarity index 97%
rename from pipelined/src/lsu/busdp.sv
rename to pipelined/src/cache/cachedp.sv
index 730309484..e61fe2a31 100644
--- a/pipelined/src/lsu/busdp.sv
+++ b/pipelined/src/cache/cachedp.sv
@@ -1,10 +1,10 @@
///////////////////////////////////////////
-// busdp.sv
+// cachedp.sv
//
// Written: Ross Thompson ross1728@gmail.com January 30, 2022
// Modified:
//
-// Purpose: Bus data path.
+// Purpose: Cache/Bus data path.
// Bus Side logic
// register the fetch data from the next level of memory.
// This register should be necessary for timing. There is no register in the uncore or
@@ -34,7 +34,7 @@
`include "wally-config.vh"
-module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
+module cachedp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
(
input logic clk, reset,
diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index 4577b4206..244b63c63 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -187,37 +187,17 @@ module ifu (
if (`IROM) begin : irom
irom irom(.clk, .reset, .Adr(CPUBusy | reset ? PCFSpill : PCNextFSpill), .ReadData(FinalInstrRawF));
- assign {BusStall, IFUBusRead} = '0;
- assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0;
end
if (`BUS) begin : bus
localparam integer WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1;
- localparam integer LINELEN = `ICACHE ? `ICACHE_LINELENINBITS : `XLEN;
localparam integer LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1;
- logic [LINELEN-1:0] FetchBuffer;
- logic [`PA_BITS-1:0] ICacheBusAdr;
- logic ICacheBusAck;
- logic SelUncachedAdr;
-
- busdp #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE)
- busdp(.clk, .reset,
- .HRDATA(HRDATA), .BusAck(IFUBusAck), .BusInit(IFUBusInit), .BusWrite(), .SelBusWord(),
- .BusRead(IFUBusRead), .HSIZE(), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .BusTransComplete(IFUTransComplete),
- .Funct3(3'b010), .HADDR(IFUHADDR), .CacheBusAdr(ICacheBusAdr),
- .WordCount(),
- .CacheFetchLine(ICacheFetchLine),
- .CacheWriteLine(1'b0), .CacheBusAck(ICacheBusAck),
- .FetchBuffer, .PAdr(PCPF),
- .SelUncachedAdr,
- .IgnoreRequest(ITLBMissF), .RW(2'b10), .CPUBusy, .Cacheable(CacheableF),
- .BusStall, .BusCommitted());
-
-
- mux2 #(32) UnCachedDataMux(.d0(FinalInstrRawF), .d1(FetchBuffer[32-1:0]),
- .s(SelUncachedAdr), .y(AllInstrRawF[31:0]));
-
-
if(`ICACHE) begin : icache
+ localparam integer LINELEN = `ICACHE ? `ICACHE_LINELENINBITS : `XLEN;
+ logic [LINELEN-1:0] FetchBuffer;
+ logic [`PA_BITS-1:0] ICacheBusAdr;
+ logic ICacheBusAck;
+ logic SelUncachedAdr;
+
cache #(.LINELEN(`ICACHE_LINELENINBITS),
.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
.NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0))
@@ -235,12 +215,39 @@ module ifu (
.NextAdr(PCNextFSpill[11:0]),
.PAdr(PCPF),
.CacheCommitted(), .InvalidateCache(InvalidateICacheM));
+ cachedp #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE)
+ cachedp(.clk, .reset,
+ .HRDATA(HRDATA), .BusAck(IFUBusAck), .BusInit(IFUBusInit), .BusWrite(), .SelBusWord(),
+ .BusRead(IFUBusRead), .HSIZE(), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .BusTransComplete(IFUTransComplete),
+ .Funct3(3'b010), .HADDR(IFUHADDR), .CacheBusAdr(ICacheBusAdr),
+ .WordCount(),
+ .CacheFetchLine(ICacheFetchLine),
+ .CacheWriteLine(1'b0), .CacheBusAck(ICacheBusAck),
+ .FetchBuffer, .PAdr(PCPF),
+ .SelUncachedAdr,
+ .IgnoreRequest(ITLBMissF), .RW(2'b10), .CPUBusy, .Cacheable(CacheableF),
+ .BusStall, .BusCommitted());
+ mux2 #(32) UnCachedDataMux(.d0(FinalInstrRawF), .d1(FetchBuffer[32-1:0]),
+ .s(SelUncachedAdr), .y(AllInstrRawF[31:0]));
end else begin : passthrough
- assign {ICacheFetchLine, ICacheBusAdr, ICacheStallF, FinalInstrRawF} = '0;
- assign ICacheAccess = CacheableF; assign ICacheMiss = CacheableF;
+ assign IFUHADDR = PCPF;
+ flopen #(`XLEN) fb(.clk, .en(IFUBusRead), .d(HRDATA), .q(AllInstrRawF[31:0]));
+
+ busfsm #(LOGBWPL) busfsm(
+ .clk, .reset, .IgnoreRequest(ITLBMissF), .RW(2'b10),
+ .BusAck(IFUBusAck), .BusInit(IFUBusInit), .CPUBusy,
+ .BusStall, .BusWrite(), .BusRead(IFUBusRead),
+ .HTRANS(IFUHTRANS), .BusCommitted());
+
+ assign IFUHBURST = 3'b0;
+ assign IFUTransComplete = IFUBusAck;
+ assign {ICacheFetchLine, ICacheStallF, FinalInstrRawF} = '0;
+ assign {ICacheMiss, ICacheAccess} = '0;
end
end else begin : nobus // block: bus
+ assign {BusStall, IFUBusRead} = '0;
+ assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0;
assign AllInstrRawF = FinalInstrRawF;
end
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 41b441738..0a2ca212c 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -208,19 +208,18 @@ module lsu (
// There are no peripherals supported.
// *** this will have to change to support TIM and bus (DH 8/25/22)
end
- if (`BUS) begin : bus
+ if (`BUS) begin : bus
localparam integer WORDSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`XLEN : 1;
- localparam integer LINELEN = `DCACHE ? `DCACHE_LINELENINBITS : `XLEN;
localparam integer LOGBWPL = `DCACHE ? $clog2(WORDSPERLINE) : 1;
- logic [LINELEN-1:0] FetchBuffer;
- logic [`PA_BITS-1:0] DCacheBusAdr;
- logic DCacheWriteLine;
- logic DCacheFetchLine;
- logic [LOGBWPL-1:0] WordCount;
-
if(`DCACHE) begin : dcache
+ localparam integer LINELEN = `DCACHE ? `DCACHE_LINELENINBITS : `XLEN;
+ logic [LINELEN-1:0] FetchBuffer;
+ logic [`PA_BITS-1:0] DCacheBusAdr;
+ logic DCacheWriteLine;
+ logic DCacheFetchLine;
+ logic [LOGBWPL-1:0] WordCount;
logic SelUncachedAdr, DCacheBusAck;
- logic SelBusWord;
+ logic SelBusWord;
cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
.NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache(
@@ -233,7 +232,7 @@ module lsu (
.CacheBusAdr(DCacheBusAdr), .ReadDataWord(ReadDataWordM),
.FetchBuffer, .CacheFetchLine(DCacheFetchLine),
.CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0));
- busdp #(WORDSPERLINE, LINELEN, LOGBWPL, `DCACHE) busdp(
+ cachedp #(WORDSPERLINE, LINELEN, LOGBWPL, `DCACHE) cachedp(
.clk, .reset,
.HRDATA, .BusAck(LSUBusAck), .BusInit(LSUBusInit), .BusWrite(LSUBusWrite),
.BusRead(LSUBusRead), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .BusTransComplete(LSUTransComplete),
@@ -248,6 +247,9 @@ module lsu (
mux2 #(`XLEN) LSUHWDATAMux(.d0(ReadDataWordM[`XLEN-1:0]), .d1(LSUWriteDataM[`XLEN-1:0]),
.s(SelUncachedAdr), .y(LSUHWDATA));
end else begin : passthrough // just needs a register to hold the value from the bus
+ assign LSUHADDR = LSUPAdrM;
+ assign LSUHSIZE = LSUFunct3M;
+
flopen #(`XLEN) fb(.clk, .en(LSUBusRead), .d(HRDATA), .q(ReadDataWordMuxM));
assign LSUHWDATA = LSUWriteDataM[`XLEN-1:0];
@@ -260,7 +262,7 @@ module lsu (
// *** possible bug - ReadDatWordM vs. ReadDataWordMuxW - is byte swapping needed for endian
assign LSUHBURST = 3'b0;
assign LSUTransComplete = LSUBusAck;
- assign {ReadDataWordM, DCacheStallM, DCacheCommittedM, DCacheFetchLine, DCacheWriteLine} = '0;
+ assign {ReadDataWordM, DCacheStallM, DCacheCommittedM} = '0;
assign {DCacheMiss, DCacheAccess} = '0;
end
end else begin: nobus // block: bus