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More trap/csr simplification

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This commit is contained in:
David Harris 2022-05-12 21:55:50 +00:00
parent 21ac969c7d
commit 5f358a37c6
3 changed files with 15 additions and 65 deletions
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13
pipelined/src/privileged/csr.sv
View File

@ -114,7 +114,6 @@ module csr #(parameter
default: NextFaultMtvalM = 0; // Ecall, interrupts default: NextFaultMtvalM = 0; // Ecall, interrupts
endcase endcase
/////////////////////////////////////////// ///////////////////////////////////////////
// Trap Vectoring // Trap Vectoring
/////////////////////////////////////////// ///////////////////////////////////////////
@ -147,7 +146,9 @@ module csr #(parameter
else if (mretM) PrivilegedNextPCM = MEPC_REGW; else if (mretM) PrivilegedNextPCM = MEPC_REGW;
else PrivilegedNextPCM = SEPC_REGW; else PrivilegedNextPCM = SEPC_REGW;
// modify CSRs ///////////////////////////////////////////
// CSRWriteValM
///////////////////////////////////////////
always_comb begin always_comb begin
// Choose either rs1 or uimm[4:0] as source // Choose either rs1 or uimm[4:0] as source
CSRSrcM = InstrM[14] ? {{(`XLEN-5){1'b0}}, InstrM[19:15]} : SrcAM; CSRSrcM = InstrM[14] ? {{(`XLEN-5){1'b0}}, InstrM[19:15]} : SrcAM;
@ -168,7 +169,9 @@ module csr #(parameter
endcase endcase
end end
// write CSRs ///////////////////////////////////////////
// CSR Write values
///////////////////////////////////////////
assign CSRAdrM = InstrM[31:20]; assign CSRAdrM = InstrM[31:20];
assign UnalignedNextEPCM = TrapM ? ((wfiM & InterruptM) ? PCM+4 : PCM) : CSRWriteValM; assign UnalignedNextEPCM = TrapM ? ((wfiM & InterruptM) ? PCM+4 : PCM) : CSRWriteValM;
assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[`XLEN-1:1], 1'b0} : {UnalignedNextEPCM[`XLEN-1:2], 2'b00}; // 3.1.15 alignment assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[`XLEN-1:1], 1'b0} : {UnalignedNextEPCM[`XLEN-1:2], 2'b00}; // 3.1.15 alignment
@ -178,6 +181,10 @@ module csr #(parameter
assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW); assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW);
assign CSRUWriteM = CSRWriteM; assign CSRUWriteM = CSRWriteM;
///////////////////////////////////////////
// CSRs
///////////////////////////////////////////
csri csri(.clk, .reset, .InstrValidNotFlushedM, .StallW, csri csri(.clk, .reset, .InstrValidNotFlushedM, .StallW,
.CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM, .CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM,
.MExtInt, .SExtInt, .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .MTimerInt, .MSwInt,

7
pipelined/src/privileged/privileged.sv
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@ -81,7 +81,7 @@ module privileged (
output logic BreakpointFaultM, EcallFaultM, wfiM, IntPendingM, BigEndianM output logic BreakpointFaultM, EcallFaultM, wfiM, IntPendingM, BigEndianM
); );
logic [`XLEN-1:0] CauseM; //, NextFaultMtvalM; logic [`XLEN-1:0] CauseM;
logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW; logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW;
logic [`XLEN-1:0] MEDELEG_REGW; logic [`XLEN-1:0] MEDELEG_REGW;
logic [11:0] MIDELEG_REGW; logic [11:0] MIDELEG_REGW;
@ -133,7 +133,7 @@ module privileged (
.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM,
.BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
.NextPrivilegeModeM, .PrivilegeModeW, .NextPrivilegeModeM, .PrivilegeModeW,
.CauseM, /*.NextFaultMtvalM,*/ .SelHPTW, .CauseM, .SelHPTW,
.STATUS_MPP, .STATUS_MPP,
.STATUS_SPP, .STATUS_TSR, .STATUS_TVM, .STATUS_SPP, .STATUS_TSR, .STATUS_TVM,
.MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW, .MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW,
@ -164,11 +164,10 @@ module privileged (
.MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW, .MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW,
.MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
.STATUS_MIE, .STATUS_SIE, .STATUS_MIE, .STATUS_SIE,
/* .PCM, .IEUAdrM, .InstrM,*/
.InstrValidM, .CommittedM, .InstrValidM, .CommittedM,
.TrapM, .MTrapM, .STrapM, .RetM, .TrapM, .MTrapM, .STrapM, .RetM,
.InterruptM, .IntPendingM, .InterruptM, .IntPendingM,
/* .PrivilegedNextPCM, */.CauseM/*MtvalM*/); .CauseM);
endmodule endmodule

60
pipelined/src/privileged/trap.sv
View File

@ -42,22 +42,15 @@ module trap (
(* mark_debug = "true" *) input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW, (* mark_debug = "true" *) input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW,
(* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW,
input logic STATUS_MIE, STATUS_SIE, input logic STATUS_MIE, STATUS_SIE,
/* input logic [`XLEN-1:0] PCM,
input logic [`XLEN-1:0] IEUAdrM,
input logic [31:0] InstrM, */
input logic InstrValidM, CommittedM, input logic InstrValidM, CommittedM,
output logic TrapM, MTrapM, STrapM, RetM, output logic TrapM, MTrapM, STrapM, RetM,
output logic InterruptM, IntPendingM, output logic InterruptM, IntPendingM,
output logic [`XLEN-1:0] /*PrivilegedNextPCM, */CauseM //NextFaultMtvalM output logic [`XLEN-1:0] CauseM
// output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW,
// input logic WriteMIPM, WriteSIPM, WriteUIPM, WriteMIEM, WriteSIEM, WriteUIEM
); );
logic MIntGlobalEnM, SIntGlobalEnM; logic MIntGlobalEnM, SIntGlobalEnM;
logic ExceptionM; logic ExceptionM;
(* mark_debug = "true" *) logic [11:0] PendingIntsM, ValidIntsM; (* mark_debug = "true" *) logic [11:0] PendingIntsM, ValidIntsM;
//logic InterruptM;
//logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector;
/////////////////////////////////////////// ///////////////////////////////////////////
// Determine pending enabled interrupts // Determine pending enabled interrupts
@ -82,45 +75,11 @@ module trap (
InstrPageFaultM | LoadPageFaultM | StoreAmoPageFaultM | InstrPageFaultM | LoadPageFaultM | StoreAmoPageFaultM |
BreakpointFaultM | EcallFaultM | BreakpointFaultM | EcallFaultM |
LoadAccessFaultM | StoreAmoAccessFaultM; LoadAccessFaultM | StoreAmoAccessFaultM;
assign TrapM = ExceptionM | InterruptM; // *** clean this up later DH assign TrapM = ExceptionM | InterruptM;
assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE); assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE);
assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED; assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED;
assign RetM = mretM | sretM; assign RetM = mretM | sretM;
/*
always_comb
if (NextPrivilegeModeM == `S_MODE) PrivilegedTrapVector = STVEC_REGW;
else PrivilegedTrapVector = MTVEC_REGW;
///////////////////////////////////////////
// Handle vectored traps (when mtvec/stvec csr value has bits [1:0] == 01)
// For vectored traps, set program counter to _tvec value + 4 times the cause code
///////////////////////////////////////////
//
// POSSIBLE OPTIMIZATION:
// From 20190608 privielegd spec page 27 (3.1.7)
// > Allowing coarser alignments in Vectored mode enables vectoring to be
// > implemented without a hardware adder circuit.
// For example, we could require m/stvec be aligned on 7 bits to let us replace the adder directly below with
// [untested] PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:7], CauseM[3:0], 4'b0000}
// However, this is program dependent, so not implemented at this time.
if(`VECTORED_INTERRUPTS_SUPPORTED) begin:vec
always_comb
if (PrivilegedTrapVector[1:0] == 2'b01 & CauseM[`XLEN-1] == 1)
PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2] + CauseM[`XLEN-3:0], 2'b00};
else
PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00};
end
else begin
assign PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00};
end
always_comb
if (TrapM) PrivilegedNextPCM = PrivilegedVectoredTrapVector;
else if (mretM) PrivilegedNextPCM = MEPC_REGW;
else PrivilegedNextPCM = SEPC_REGW;
*/
/////////////////////////////////////////// ///////////////////////////////////////////
// Cause priority defined in table 3.7 of 20190608 privileged spec // Cause priority defined in table 3.7 of 20190608 privileged spec
// Exceptions are of lower priority than all interrupts (3.1.9) // Exceptions are of lower priority than all interrupts (3.1.9)
@ -146,19 +105,4 @@ module trap (
else if (LoadAccessFaultM) CauseM = 5; else if (LoadAccessFaultM) CauseM = 5;
else if (StoreAmoAccessFaultM) CauseM = 7; else if (StoreAmoAccessFaultM) CauseM = 7;
else CauseM = 0; else CauseM = 0;
/* always_comb
if (InstrPageFaultM) NextFaultMtvalM = PCM;
else if (InstrAccessFaultM) NextFaultMtvalM = PCM;
else if (IllegalInstrFaultM) NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM};
else if (InstrMisalignedFaultM) NextFaultMtvalM = IEUAdrM;
else if (EcallFaultM) NextFaultMtvalM = 0;
else if (BreakpointFaultM) NextFaultMtvalM = PCM;
else if (LoadMisalignedFaultM) NextFaultMtvalM = IEUAdrM;
else if (StoreAmoMisalignedFaultM) NextFaultMtvalM = IEUAdrM;
else if (LoadPageFaultM) NextFaultMtvalM = IEUAdrM;
else if (StoreAmoPageFaultM) NextFaultMtvalM = IEUAdrM;
else if (LoadAccessFaultM) NextFaultMtvalM = IEUAdrM;
else if (StoreAmoAccessFaultM) NextFaultMtvalM = IEUAdrM;
else NextFaultMtvalM = 0; */
endmodule endmodule