From 5efd5958e7c804fbb1a3b4c773e48746b34fc473 Mon Sep 17 00:00:00 2001 From: bbracker Date: Mon, 22 Mar 2021 15:40:29 -0400 Subject: [PATCH] added delays to uart AHB signals --- wally-pipelined/src/uncore/uart.sv | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/wally-pipelined/src/uncore/uart.sv b/wally-pipelined/src/uncore/uart.sv index 373674867..e1b1ef941 100644 --- a/wally-pipelined/src/uncore/uart.sv +++ b/wally-pipelined/src/uncore/uart.sv @@ -45,11 +45,10 @@ module uart ( logic [7:0] Din, Dout; // rename processor interface signals to match PC16550D and provide one-byte interface - always_ff @(posedge HCLK) begin - MEMRb <= ~(HSELUART & ~HWRITE); - MEMWb <= ~(HSELUART & HWRITE); - A <= HADDR[2:0]; - end + flopr #(1) memreadreg(HCLK, ~HRESETn, ~(HSELUART & ~HWRITE), MEMRb); + flopr #(1) memwritereg(HCLK, ~HRESETn, ~(HSELUART & HWRITE), MEMWb); + flopr #(3) haddrreg(HCLK, ~HRESETn, HADDR[2:0], A); + assign HRESPUART = 0; // OK assign HREADYUART = 1; // should idle high during address phase and respond high when done; will need to be modified if UART ever needs more than 1 cycle to do something