Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

fdivsqrtfsm conditional on IDIV

Browse Source
This commit is contained in:
David Harris 2022-12-27 22:15:45 -08:00
commit 5ee44b7405
3 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
pipelined/config/shared/wally-shared.vh
View File

@ -110,7 +110,7 @@
// division constants // division constants
`define RADIX 32'h2 `define RADIX 32'h2
`define DIVCOPIES 32'h1 `define DIVCOPIES 32'h4
`define DIVLEN ((`NF < `XLEN) ? (`XLEN) : `NF+3) `define DIVLEN ((`NF < `XLEN) ? (`XLEN) : `NF+3)
// `define DIVN (`NF < `XLEN ? `XLEN : `NF+1) // length of input // `define DIVN (`NF < `XLEN ? `XLEN : `NF+1) // length of input
`define DIVN (`NF<`XLEN ? `XLEN : (`NF + 3)) // length of input `define DIVN (`NF<`XLEN ? `XLEN : (`NF + 3)) // length of input

2
pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv
View File

@ -105,7 +105,7 @@ module fdivsqrtfsm(
always_comb begin always_comb begin
if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2 if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2
else fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs else fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
if (`IDIV_ON_FPU) cycles = MDUE ? (nE + 1) : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES); if (`IDIV_ON_FPU) cycles = MDUE ? ((nE + 1)/`DIVCOPIES)) : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
else cycles = (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES); else cycles = (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
end end

1
pipelined/testbench/tests.vh
View File

@ -138,6 +138,7 @@ string tvpaths[] = '{
string imperas32f[] = '{ string imperas32f[] = '{
`IMPERASTEST, `IMPERASTEST,
"rv32i_m/F/FSQRT-S-DYN-RDN-01",
"rv32i_m/F/FADD-S-DYN-RDN-01", "rv32i_m/F/FADD-S-DYN-RDN-01",
"rv32i_m/F/FADD-S-DYN-RMM-01", "rv32i_m/F/FADD-S-DYN-RMM-01",
"rv32i_m/F/FADD-S-DYN-RNE-01", "rv32i_m/F/FADD-S-DYN-RNE-01",