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fdivsqrtfsm conditional on IDIV
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commit
5ee44b7405
@ -110,7 +110,7 @@
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// division constants
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// division constants
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`define RADIX 32'h2
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`define RADIX 32'h2
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`define DIVCOPIES 32'h1
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`define DIVCOPIES 32'h4
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`define DIVLEN ((`NF < `XLEN) ? (`XLEN) : `NF+3)
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`define DIVLEN ((`NF < `XLEN) ? (`XLEN) : `NF+3)
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// `define DIVN (`NF < `XLEN ? `XLEN : `NF+1) // length of input
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// `define DIVN (`NF < `XLEN ? `XLEN : `NF+1) // length of input
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`define DIVN (`NF<`XLEN ? `XLEN : (`NF + 3)) // length of input
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`define DIVN (`NF<`XLEN ? `XLEN : (`NF + 3)) // length of input
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@ -105,7 +105,7 @@ module fdivsqrtfsm(
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always_comb begin
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always_comb begin
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if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2
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if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2
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else fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
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else fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
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if (`IDIV_ON_FPU) cycles = MDUE ? (nE + 1) : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
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if (`IDIV_ON_FPU) cycles = MDUE ? ((nE + 1)/`DIVCOPIES)) : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
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else cycles = (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
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else cycles = (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
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end
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end
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@ -138,6 +138,7 @@ string tvpaths[] = '{
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string imperas32f[] = '{
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string imperas32f[] = '{
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`IMPERASTEST,
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`IMPERASTEST,
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"rv32i_m/F/FSQRT-S-DYN-RDN-01",
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"rv32i_m/F/FADD-S-DYN-RDN-01",
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"rv32i_m/F/FADD-S-DYN-RDN-01",
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"rv32i_m/F/FADD-S-DYN-RMM-01",
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"rv32i_m/F/FADD-S-DYN-RMM-01",
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"rv32i_m/F/FADD-S-DYN-RNE-01",
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"rv32i_m/F/FADD-S-DYN-RNE-01",
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