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fdivsqrt post processing simplification
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@ -101,7 +101,7 @@ module fdivsqrtpostproc(
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if (`IDIV_ON_FPU) begin // Int supported
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if (`IDIV_ON_FPU) begin // Int supported
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logic [`DIVBLEN:0] NormShiftM;
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logic [`DIVBLEN:0] NormShiftM;
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logic [`DIVb+3:0] IntQuotM, IntRemM, NormRemM, NormRemDM;
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logic [`DIVb+3:0] IntQuotM, IntRemM, NormRemM, NormRemDM, NormQuotM;
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assign W = $signed(Sum) >>> `LOGR;
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assign W = $signed(Sum) >>> `LOGR;
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assign DM = {4'b0001, D};
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assign DM = {4'b0001, D};
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@ -109,6 +109,7 @@ module fdivsqrtpostproc(
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// Integer remainder: sticky and sign correction muxes
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// Integer remainder: sticky and sign correction muxes
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mux2 #(`DIVb+4) normremdmux(W, W+DM, NegStickyM, NormRemDM);
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mux2 #(`DIVb+4) normremdmux(W, W+DM, NegStickyM, NormRemDM);
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mux2 #(`DIVb+4) normremsmux(NormRemDM, -NormRemDM, AsM, NormRemM);
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mux2 #(`DIVb+4) normremsmux(NormRemDM, -NormRemDM, AsM, NormRemM);
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mux2 #(`DIVb+4) quotresmux({3'b000, PreQmM}, {3'b111, -PreQmM}, NegQuotM, NormQuotM);
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// special case logic
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// special case logic
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always_comb
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always_comb
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@ -123,12 +124,6 @@ module fdivsqrtpostproc(
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if (WZeroM) begin
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if (WZeroM) begin
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PreIntQuotM = weq0M ? {3'b000, FirstU} : {3'b000, FirstUM};
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PreIntQuotM = weq0M ? {3'b000, FirstU} : {3'b000, FirstUM};
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IntRemM = '0;
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IntRemM = '0;
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/* if (weq0M) begin
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PreIntQuotM = {3'b000, FirstU};
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end else begin
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PreIntQuotM = {3'b000, FirstUM};
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IntRemM = '0;
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end */
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end else begin
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end else begin
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PreIntQuotM = {3'b000, PreQmM};
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PreIntQuotM = {3'b000, PreQmM};
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IntRemM = NormRemM;
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IntRemM = NormRemM;
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