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fdivsqrt post processing simplification

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This commit is contained in:
David Harris 2022-12-31 05:36:09 -08:00
parent 6832b9d9f6
commit 5edc925dff
1 changed files with 2 additions and 7 deletions
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pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
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@ -101,7 +101,7 @@ module fdivsqrtpostproc(
if (`IDIV_ON_FPU) begin // Int supported if (`IDIV_ON_FPU) begin // Int supported
logic [`DIVBLEN:0] NormShiftM; logic [`DIVBLEN:0] NormShiftM;
logic [`DIVb+3:0] IntQuotM, IntRemM, NormRemM, NormRemDM; logic [`DIVb+3:0] IntQuotM, IntRemM, NormRemM, NormRemDM, NormQuotM;
assign W = $signed(Sum) >>> `LOGR; assign W = $signed(Sum) >>> `LOGR;
assign DM = {4'b0001, D}; assign DM = {4'b0001, D};
@ -109,6 +109,7 @@ module fdivsqrtpostproc(
// Integer remainder: sticky and sign correction muxes // Integer remainder: sticky and sign correction muxes
mux2 #(`DIVb+4) normremdmux(W, W+DM, NegStickyM, NormRemDM); mux2 #(`DIVb+4) normremdmux(W, W+DM, NegStickyM, NormRemDM);
mux2 #(`DIVb+4) normremsmux(NormRemDM, -NormRemDM, AsM, NormRemM); mux2 #(`DIVb+4) normremsmux(NormRemDM, -NormRemDM, AsM, NormRemM);
mux2 #(`DIVb+4) quotresmux({3'b000, PreQmM}, {3'b111, -PreQmM}, NegQuotM, NormQuotM);
// special case logic // special case logic
always_comb always_comb
@ -123,12 +124,6 @@ module fdivsqrtpostproc(
if (WZeroM) begin if (WZeroM) begin
PreIntQuotM = weq0M ? {3'b000, FirstU} : {3'b000, FirstUM}; PreIntQuotM = weq0M ? {3'b000, FirstU} : {3'b000, FirstUM};
IntRemM = '0; IntRemM = '0;
/* if (weq0M) begin
PreIntQuotM = {3'b000, FirstU};
end else begin
PreIntQuotM = {3'b000, FirstUM};
IntRemM = '0;
end */
end else begin end else begin
PreIntQuotM = {3'b000, PreQmM}; PreIntQuotM = {3'b000, PreQmM};
IntRemM = NormRemM; IntRemM = NormRemM;