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Have a rough working multi manager!

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This commit is contained in:
Ross Thompson 2022-08-29 17:11:27 -05:00
parent 4f40bd07c3
commit 5eb1fff27d
2 changed files with 7 additions and 2 deletions
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5
pipelined/src/lsu/lsu.sv
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@ -83,6 +83,7 @@ module lsu (
(* mark_debug = "true" *) output logic [2:0] LSUHSIZE, (* mark_debug = "true" *) output logic [2:0] LSUHSIZE,
(* mark_debug = "true" *) output logic [2:0] LSUHBURST, (* mark_debug = "true" *) output logic [2:0] LSUHBURST,
(* mark_debug = "true" *) output logic [1:0] LSUHTRANS, (* mark_debug = "true" *) output logic [1:0] LSUHTRANS,
(* mark_debug = "true" *) output logic [`XLEN/8-1:0] LSUHWSTRB,
(* mark_debug = "true" *) output logic LSUTransComplete, (* mark_debug = "true" *) output logic LSUTransComplete,
// page table walker // page table walker
input logic [`XLEN-1:0] SATP_REGW, // from csr input logic [`XLEN-1:0] SATP_REGW, // from csr
@ -277,7 +278,9 @@ module lsu (
assign LSUHSIZE = LSUFunct3M; assign LSUHSIZE = LSUFunct3M;
flopen #(`XLEN) fb(.clk, .en(CaptureEn), .d(HRDATA), .q(ReadDataWordM)); flopen #(`XLEN) fb(.clk, .en(CaptureEn), .d(HRDATA), .q(ReadDataWordM));
assign LSUHWDATA = LSUWriteDataM[`XLEN-1:0];
flop #(`XLEN) wdreg(clk, LSUWriteDataM, LSUHWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
flop #(`XLEN/8) HWSTRBReg(clk, ByteMaskM, LSUHWSTRB);
/* -----\/----- EXCLUDED -----\/----- /* -----\/----- EXCLUDED -----\/-----
busfsm #(LOGBWPL) busfsm( busfsm #(LOGBWPL) busfsm(

4
pipelined/src/wally/wallypipelinedcore.sv
View File

@ -147,6 +147,7 @@ module wallypipelinedcore (
logic LSUBusWrite; logic LSUBusWrite;
logic LSUBusAck, LSUBusInit; logic LSUBusAck, LSUBusInit;
logic [`XLEN-1:0] LSUHWDATA; logic [`XLEN-1:0] LSUHWDATA;
logic [`XLEN/8-1:0] LSUHWSTRB;
logic LSUHWRITE; logic LSUHWRITE;
logic LSUHREADY; logic LSUHREADY;
@ -264,7 +265,7 @@ module wallypipelinedcore (
.ReadDataW, .FlushDCacheM, .ReadDataW, .FlushDCacheM,
// connected to ahb (all stay the same) // connected to ahb (all stay the same)
.LSUHADDR, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusInit, .LSUHADDR, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusInit,
.HRDATA, .LSUHWDATA, .LSUHSIZE, .LSUHBURST, .LSUHTRANS, .LSUTransComplete, .HRDATA, .LSUHWDATA, .LSUHWSTRB, .LSUHSIZE, .LSUHBURST, .LSUHTRANS, .LSUTransComplete,
.LSUHWRITE, .LSUHREADY, .LSUHWRITE, .LSUHREADY,
// connect to csr or privilege and stay the same. // connect to csr or privilege and stay the same.
@ -333,6 +334,7 @@ module wallypipelinedcore (
// Signals from Data Cache // Signals from Data Cache
.LSUHADDR, .LSUHADDR,
.LSUHWDATA, .LSUHWDATA,
.LSUHWSTRB,
.LSUHSIZE, .LSUHSIZE,
.LSUHBURST, .LSUHBURST,
.LSUHTRANS, .LSUHTRANS,