From 5e9a39e7554a54078a5973f35ce50912f364527d Mon Sep 17 00:00:00 2001
From: bbracker <bbracker@hmc.edu>
Date: Tue, 7 Sep 2021 19:14:39 -0400
Subject: [PATCH] fixed bug where M mode was sensitive to S mode traps

---
 .../regression/wave-dos/peripheral-waves.do         | 13 -------------
 wally-pipelined/src/privileged/csri.sv              |  2 +-
 wally-pipelined/src/privileged/trap.sv              |  2 +-
 wally-pipelined/testbench/testbench-linux.sv        | 12 ++++++------
 4 files changed, 8 insertions(+), 21 deletions(-)

diff --git a/wally-pipelined/regression/wave-dos/peripheral-waves.do b/wally-pipelined/regression/wave-dos/peripheral-waves.do
index d8371ff7b..2da82b869 100644
--- a/wally-pipelined/regression/wave-dos/peripheral-waves.do
+++ b/wally-pipelined/regression/wave-dos/peripheral-waves.do
@@ -112,16 +112,3 @@ add wave -hex /testbench/dut/uncore/gpio/gpio/*
 
 # everything else
 add wave -hex -r /testbench/*
-
-# appearance
-TreeUpdate [SetDefaultTree]
-WaveRestoreZoom {0 ps} {100 ps}
-configure wave -namecolwidth 250
-configure wave -valuecolwidth 150
-configure wave -justifyvalue left
-configure wave -signalnamewidth 0
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-set DefaultRadix hexadecimal
diff --git a/wally-pipelined/src/privileged/csri.sv b/wally-pipelined/src/privileged/csri.sv
index bf7e5f541..3b54d871a 100644
--- a/wally-pipelined/src/privileged/csri.sv
+++ b/wally-pipelined/src/privileged/csri.sv
@@ -78,7 +78,7 @@ module csri #(parameter
       assign MIP_WRITE_MASK = 12'h000;
       assign SIP_WRITE_MASK = 12'h000;
     end
-    always @(posedge clk, posedge reset) begin
+    always @(posedge clk, posedge reset) begin // *** I strongly feel that IntInM should go directly to IP_REGW -- Ben 9/7/21
       if (reset)          IP_REGW_writeable <= 10'b0;
       else if (WriteMIPM) IP_REGW_writeable <= (CSRWriteValM[9:0] & MIP_WRITE_MASK[9:0]) | IntInM[9:0]; // MTIP unclearable
       else if (WriteSIPM) IP_REGW_writeable <= (CSRWriteValM[9:0] & SIP_WRITE_MASK[9:0]) | IntInM[9:0]; // MTIP unclearable
diff --git a/wally-pipelined/src/privileged/trap.sv b/wally-pipelined/src/privileged/trap.sv
index e9a9fd115..6bb41597f 100644
--- a/wally-pipelined/src/privileged/trap.sv
+++ b/wally-pipelined/src/privileged/trap.sv
@@ -63,7 +63,7 @@ module trap (
   // & with a M stage valid bit to avoid interrupts from interrupt a nonexistent flushed instruction (in the M stage)
   // & with ~CommittedM to make sure MEPC isn't chosen so as to rerun the same instr twice
   assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) || STATUS_MIE; // if M ints enabled or lower priv 3.1.9
-  assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) || STATUS_SIE; // if S ints enabled or lower priv 3.1.9
+  assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) || ((PrivilegeModeW == `S_MODE) && STATUS_SIE); // if in lower priv mode, or if S ints enabled and not in higher priv mode 3.1.9
   assign PendingIntsM = ((MIP_REGW & MIE_REGW) & ({12{MIntGlobalEnM}} & 12'h888)) | ((SIP_REGW & SIE_REGW) & ({12{SIntGlobalEnM}} & 12'h222));
   assign PendingInterruptM = (|PendingIntsM) & InstrValidM;  
   assign InterruptM = PendingInterruptM & ~CommittedM;
diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv
index d3d492b5e..fd4ce1ac2 100644
--- a/wally-pipelined/testbench/testbench-linux.sv
+++ b/wally-pipelined/testbench/testbench-linux.sv
@@ -250,13 +250,13 @@ module testbench();
             forcedInterrupt = 1;
             if(ExpectedIntType == 0) begin
               force dut.hart.priv.SwIntM = 1'b1;
-              $display("Force SwIntM");
+              $display("Activate spoofed SwIntM");
             end else if(ExpectedIntType == 4) begin
               force dut.hart.priv.TimerIntM = 1'b1;
-              $display("Force TimeIntM");
+              $display("Activate spoofed TimeIntM");
             end else if(ExpectedIntType == 8) begin
               force dut.hart.priv.ExtIntM = 1'b1;
-              $display("Force ExtIntM");
+              $display("Activate spoofed ExtIntM");
             end else forcedInterrupt = 0;
           end      
           NumCSRM++;      
@@ -341,15 +341,15 @@ module testbench();
           forcedInterrupt = 0;
           if(ExpectedIntType == 0) begin
             force dut.hart.priv.SwIntM = 1'b0;
-            $display("Force SwIntM");
+            $display("Deactivate spoofed SwIntM");
           end
           else if(ExpectedIntType == 4) begin
             force dut.hart.priv.TimerIntM = 1'b0;
-            $display("Force TimeIntM");
+            $display("Deactivate spoofed TimeIntM");
           end
           else if(ExpectedIntType == 8) begin
             force dut.hart.priv.ExtIntM = 1'b0;
-            $display("Force ExtIntM");
+            $display("Deactivate spoofed ExtIntM");
           end
         end
       end