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working makefile for embench and removed testbench-f64

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DTowersM 2022-05-26 00:08:18 +00:00
parent 7024293a59
commit 5e87506772
3 changed files with 31 additions and 139 deletions
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38
benchmarks/embench/Makefile
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@ -1,15 +1,37 @@
# Makefile added 1/20/22 David_Harris@hmc.edu
# Compile Embench for Wally
all: Makefile
../../addins/embench-iot/build_all.py --arch riscv32 --chip generic --board ri5cyverilator --cflags "-O2 -march=rv32i -mabi=ilp32 -mcmodel=medany" --cc riscv64-unknown-elf-gcc
./benchmark_size.py
./benchmark_speed.py
all: build sim
# view with
# more `ls -t | head -1`
allClean: clean all
build:
../../addins/embench-iot/build_all.py --builddir=bd_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-nostartfiles"
../../addins/embench-iot/build_all.py --builddir=bd_size --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostdlib" --cflags="-nostdlib" --dummy-libs="libgcc libm libc crt0"
sim: size speed
size:
../../addins/embench-iot/benchmark_size.py --builddir=bd_size
speed:
../../addins/embench-iot/benchmark_speed.py --builddir=bd_speed --target-module run_wally --cpu-mhz=50
objdump:
riscv64-unknown-elf-objdump -S ../../addins/embench-iot/bd_speed/src/aha-mont64/aha-mont64 > ../../addins/embench-iot/bd_speed/src/aha-mont64/aha-mont64.objdump
riscv64-unknown-elf-objdump -S ../../addins/embench-iot/bd_speed/src/cubic/cubic > ../../addins/embench-iot/bd_speed/src/cubic/cubic.objdump
riscv64-unknown-elf-objdump -S ../../addins/embench-iot/bd_speed/src/md5sum/md5sum > ../../addins/embench-iot/bd_speed/src/md5sum/md5sum.objdump
riscv64-unknown-elf-objdump -S ../../addins/embench-iot/bd_speed/src/statemate/statemate > ../../addins/embench-iot/bd_speed/src/statemate/statemate.objdump
clean:
rm -rf ../../addins/embench-iot/bd_speed/
rm -rf ../../addins/embench-iot/bd_size/
# std:
# ../../addins/embench-iot/build_all.py --builddir=bd_std --arch riscv32 --chip generic --board rv32wallyverilog --cc riscv64-unknown-elf-gcc --cflags="-v -c -O2 -ffunction-sections -march=rv32imac -mabi=ilp32" --ldflags="-Wl,-gc-sections -v -march=rv32imac -mabi=ilp32 ../../../../../benchmarks/embench/tohost.S -T../../../config/riscv32/boards/rv32wallyverilog/link.ld" --user-libs="-lm"
# riscv64-unknown-elf-objdump -D ../../addins/embench-iot/bd_std/src/aha-mont64/aha-mont64 > ../../addins/embench-iot/bd_std/src/aha-mont64/aha-mont64.objdump
# --dummy-libs="libgcc libm libc"
# --cflags "-O2 -g -nostartfiles"
# ../../addins/embench-iot/build_all.py --arch riscv32 --chip generic --board rv32wallyverilog --cc riscv64-unknown-elf-gcc --cflags="-c -Os -ffunction-sections -nostdlib -march=rv32imac -mabi=ilp32" --ldflags="-Wl,-gc-sections -nostdlib -march=rv32imac -mabi=ilp32 -T../../../config/riscv32/boards/rv32wallyverilog/link.ld" --dummy-libs="libgcc libm libc"
# --user-libs="-lm"
# riscv64-unknown-elf-gcc -O2 -g -nostartfiles -I/home/harris/riscv-wally/addins/embench-iot/support -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32/boards/ri5cyverilator -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32/chips/generic -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32 -DCPU_MHZ=1 -DWARMUP_HEAT=1 -o main.o /home/harris/riscv-wally/addins/embench-iot/support/main.c

7
benchmarks/embench/Makefile~
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# Makefile added 1/20/22 David_Harris@hmc.edu
# Compile Embench for Wally
all: Makefile
./build_all.py --arch riscv32 --chip generic --board ri5cyverilator --cc riscv64-unknown-elf-gcc
./benchmark_size.py
./benchmark_speed.py

123
pipelined/testbench/testbench-f64.sv
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// testbench
module testbench ();
logic [63:0] op1;
logic [63:0] op2;
logic [2:0] FOpCtrlE;
logic [2:0] FrmE;
logic op_type;
logic FmtE;
logic OvEn;
logic UnEn;
logic XSgnE, YSgnE, ZSgnE;
logic XSgnM, YSgnM;
logic [10:0] XExpE, YExpE, ZExpE;
logic [10:0] XExpM, YExpM, ZExpM;
logic [52:0] XManE, YManE, ZManE;
logic [52:0] XManM, YManM, ZManM;
logic [10:0] BiasE;
logic XNaNE, YNaNE, ZNaNE;
logic XNaNM, YNaNM, ZNaNM;
logic XSNaNE, YSNaNE, ZSNaNE;
logic XSNaNM, YSNaNM, ZSNaNM;
logic XDenormE, YDenormE, ZDenormE;
logic XZeroE, YZeroE, ZZeroE;
logic XZeroM, YZeroM, ZZeroM;
logic XInfE, YInfE, ZInfE;
logic XInfM, YInfM, ZInfM;
logic XExpMaxE;
logic XNormE;
logic FDivBusyE;
logic start;
logic reset;
logic XDenorm;
logic YDenorm;
logic [63:0] AS_Result;
logic [4:0] Flags;
logic Denorm;
logic done;
logic clk;
logic [63:0] yexpected;
logic [63:0] vectornum, errors; // bookkeeping variables
logic [199:0] testvectors[50000:0]; // array of testvectors
logic [7:0] flags_expected;
integer handle3;
integer desc3;
// instantiate device under test
unpack unpack(.X(op1), .Y(op2), .Z(64'h0), .FOpCtrlE, .FmtE,
.XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE,
.XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE,
.XZeroE, .YZeroE, .ZZeroE, .BiasE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .XNormE);
fpdiv fdivsqrt (.op1, .op2, .rm(FrmE[1:0]), .op_type(FOpCtrlE[0]),
.reset, .clk, .start, .P(~FmtE), .OvEn(1'b0), .UnEn(1'b0),
.XNaNQ(XNaNE), .YNaNQ(YNaNE), .XInfQ(XInfE), .YInfQ(YInfE), .XZeroQ(XZeroE), .YZeroQ(YZeroE),
.FDivBusyE, .done(done), .AS_Result(AS_Result), .Flags(Flags));
// current fpdivsqrt does not operation on denorms yet
assign Denorm = XDenormE | YDenormE | Flags[3];
// generate clock to sequence tests
always
begin
clk = 1; # 5; clk = 0; # 5;
end
initial
begin
handle3 = $fopen("f64_div_rne.out");
$readmemh("../testbench/fp/vectors/f64_div_rne.tv", testvectors);
vectornum = 0; errors = 0;
start = 1'b0;
// reset
reset = 1; #27; reset = 0;
end
initial
begin
desc3 = handle3;
// Operation (if applicable)
#0 op_type = 1'b0;
// Precision (32-bit or 64-bit)
#0 FmtE = 1'b1;
// From fctrl logic to dictate operation
#0 FOpCtrlE = 3'b000;
// Rounding Mode
#0 FrmE = 3'b000;
// Trap masking (n/a for RISC-V)
#0 OvEn = 1'b0;
#0 UnEn = 1'b0;
end
always @(posedge clk)
begin
if (~reset)
begin
#0; {op1, op2, yexpected, flags_expected} = testvectors[vectornum];
#50 start = 1'b1;
repeat (2)
@(posedge clk);
// deassert start after 2 cycles
start = 1'b0;
repeat (10)
@(posedge clk);
$fdisplay(desc3, "%h_%h_%h_%b_%b | %h_%b", op1, op2, AS_Result, Flags, Denorm, yexpected, (AS_Result==yexpected));
vectornum = vectornum + 1;
if (testvectors[vectornum] === 200'bx) begin
$display("%d tests completed", vectornum);
$finish;
end
end // if (~reset)
$display("%d vectors processed", vectornum);
end // always @ (posedge clk)
endmodule // tb