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https://github.com/openhwgroup/cvw
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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commit
5e3f2ce5d5
@ -474,18 +474,18 @@ module testbench();
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end
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end
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string PCtextD,PCtextE,PCtextM,PCtext2;
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string PCtextD,PCtextE,PCtextM,PCtext2;
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//always_ff @(posedge clk, posedge reset)
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always_ff @(posedge clk, posedge reset)
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// if (reset) begin
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if (reset) begin
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// PCtextE <= #1 "(reset)";
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PCtextE = "(reset)";
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// PCtextM <= #1 "(reset)";
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PCtextM = "(reset)";
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// end else begin
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end else begin
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// if (~dut.hart.StallE)
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if (~dut.hart.StallM)
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// if (dut.hart.FlushE) PCtextE <= #1 "(flushed)";
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if (dut.hart.FlushM) PCtextM = "(flushed)";
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// else PCtextE <= #1 PCtextD;
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else PCtextM = PCtextE;
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// if (~dut.hart.StallM)
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if (~dut.hart.StallE)
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// if (dut.hart.FlushM) PCtextM <= #1 "(flushed)";
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if (dut.hart.FlushE) PCtextE = "(flushed)";
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// else PCtextM <= #1 PCtextE;
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else PCtextE = PCtextD;
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// end
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end
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initial begin
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initial begin
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