diff --git a/pipelined/regression/testfloat.do b/pipelined/regression/testfloat.do
index 641781354..455f82663 100644
--- a/pipelined/regression/testfloat.do
+++ b/pipelined/regression/testfloat.do
@@ -39,7 +39,7 @@ vsim -voptargs=+acc work.testbenchfp -G TEST=$2 -suppress 4014
 view wave
 #-- display input and output signals as hexidecimal values
 #do ./wave-dos/peripheral-waves.do
-#add log -recursive /*
+add log -recursive /*
 #do wave.do deal with when ready
 
 do wave-fpu.do
diff --git a/pipelined/regression/wave-fpu.do b/pipelined/regression/wave-fpu.do
index cb2622b4a..fc8f7a351 100644
--- a/pipelined/regression/wave-fpu.do
+++ b/pipelined/regression/wave-fpu.do
@@ -36,5 +36,6 @@ add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/*
 add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtpreproc/*
 add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtpreproc/expcalc/*
 add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtfsm/*
+add wave -group {Sqrt} -noupdate -recursive /testbenchfp/fdivsqrt/fdivsqrt/*
 add wave -group {Testbench} -noupdate /testbenchfp/*
 add wave -group {Testbench} -noupdate /testbenchfp/readvectors/*
diff --git a/pipelined/src/fpu/fdivsqrtstage4.sv b/pipelined/src/fpu/fdivsqrtstage4.sv
index 02d99153f..a8457b951 100644
--- a/pipelined/src/fpu/fdivsqrtstage4.sv
+++ b/pipelined/src/fpu/fdivsqrtstage4.sv
@@ -60,7 +60,7 @@ module fdivsqrtstage4 (
 	// 0010 = -1
 	// 0001 = -2
   qsel4 qsel4(.D, .WS, .WC, .Sqrt(SqrtM), .q);
-  fgen4 fgen4(.s(q), .C, .S, .SM, .F);
+  fgen4 fgen4(.s(q), .C({4'b1111, C}), .S({3'b000, S}), .SM({3'b000, SM}), .F);
 
   always_comb
   case (q)
@@ -78,7 +78,7 @@ module fdivsqrtstage4 (
   csa #(`DIVb+4) csa(WS, WC, AddIn, |q[3:2]&~SqrtM, WSA, WCA);
  
   otfc4 otfc4(.q, .Q, .QM, .QNext, .QMNext);
-  sotfc4 sotfc4(.s(q), .Sqrt(SqrtM), .C, .S, .SM, .SNext, .SMNext);
+  sotfc4 sotfc4(.s(q), .Sqrt(SqrtM), .C({1'b1, C}), .S, .SM, .SNext, .SMNext);
 endmodule
 
 
diff --git a/pipelined/src/fpu/otfc.sv b/pipelined/src/fpu/otfc.sv
index b2d1310ff..d006278a5 100644
--- a/pipelined/src/fpu/otfc.sv
+++ b/pipelined/src/fpu/otfc.sv
@@ -147,9 +147,9 @@ endmodule
 module sotfc4(
   input  logic [3:0]   s,
   input  logic         Sqrt,
-  input  logic [`DIVb+3:0] S, SM,
-  input  logic [`DIVb+3:0] C,
-  output logic [`DIVb+3:0] SNext, SMNext
+  input  logic [`DIVb:0] S, SM,
+  input  logic [`DIVb:0] C,
+  output logic [`DIVb:0] SNext, SMNext
 );
   //  The on-the-fly converter transfers the square root 
   //  bits to the quotient as they come.
diff --git a/pipelined/src/fpu/qsel.sv b/pipelined/src/fpu/qsel.sv
index 27efe4d7f..9b6b36115 100644
--- a/pipelined/src/fpu/qsel.sv
+++ b/pipelined/src/fpu/qsel.sv
@@ -112,12 +112,12 @@ module qsel4 (
 	logic [3:0] QSel4[1023:0];
 
   always_comb begin 
-    integer d, w, i, w2;
-    for(d=0; d<8; d++)
+    integer a, w, i, w2;
+    for(a=0; a<8; a++)
       for(w=0; w<128; w++)begin
-        i = d*128+w;
+        i = a*128+w;
         w2 = w-128*(w>=64); // convert to two's complement
-        case(d)
+        case(a)
           0: if($signed(w2)>=$signed(12))      QSel4[i] = 4'b1000;
             else if(w2>=4)   QSel4[i] = 4'b0100; 
             else if(w2>=-4)  QSel4[i] = 4'b0000;