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Fixed bug Kip found.

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The no cache and no bus versions lacked assignment of CacheCommittedF in the IFU.
This commit is contained in:
Ross Thompson 2022-12-06 10:37:45 -06:00
parent 1a9c932157
commit 5dbcf8fb10
1 changed files with 2 additions and 1 deletions
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3
pipelined/src/ifu/ifu.sv
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@ -262,6 +262,7 @@ module ifu (
.HWSTRB(), .BusRW, .ByteMask(), .WriteData('0), .HWSTRB(), .BusRW, .ByteMask(), .WriteData('0),
.CPUBusy, .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer)); .CPUBusy, .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer));
assign CacheCommittedF = '0;
if(`IROM_SUPPORTED) mux2 #(32) UnCachedDataMux2(FetchBuffer, IROMInstrF, SelIROM, InstrRawF); if(`IROM_SUPPORTED) mux2 #(32) UnCachedDataMux2(FetchBuffer, IROMInstrF, SelIROM, InstrRawF);
else assign InstrRawF = FetchBuffer; else assign InstrRawF = FetchBuffer;
assign IFUHBURST = 3'b0; assign IFUHBURST = 3'b0;
@ -269,7 +270,7 @@ module ifu (
assign {ICacheMiss, ICacheAccess} = '0; assign {ICacheMiss, ICacheAccess} = '0;
end end
end else begin : nobus // block: bus end else begin : nobus // block: bus
assign BusStall = '0; assign {BusStall, CacheCommittedF} = '0;
assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0; assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0;
assign InstrRawF = IROMInstrF; assign InstrRawF = IROMInstrF;
end end