diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index 04c7b96a7..74e0900a5 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -102,9 +102,9 @@ module testbench;
         "arch64a":      if (P.A_SUPPORTED)        tests = arch64a;
         "arch64f":      if (P.F_SUPPORTED)        tests = arch64f;
         "arch64d":      if (P.D_SUPPORTED)        tests = arch64d;  
-        "arch64f_fma":      if (P.F_SUPPORTED)    tests = arch64f_fma;
-        "arch64d_fma":      if (P.D_SUPPORTED)    tests = arch64d_fma;  
-        "arch64zi":     if (P.ZIFENCEI_SUPPORTED) tests = arch64zi;
+        "arch64f_fma":  if (P.F_SUPPORTED)        tests = arch64f_fma;
+        "arch64d_fma":  if (P.D_SUPPORTED)        tests = arch64d_fma;  
+        "arch64zifencei":  if (P.ZIFENCEI_SUPPORTED) tests = arch64zifencei;
         "imperas64i":                             tests = imperas64i;
         "imperas64f":   if (P.F_SUPPORTED)        tests = imperas64f;
         "imperas64d":   if (P.D_SUPPORTED)        tests = imperas64d;
@@ -124,6 +124,8 @@ module testbench;
         "arch64zbb":     if (P.ZBB_SUPPORTED)     tests = arch64zbb;
         "arch64zbc":     if (P.ZBC_SUPPORTED)     tests = arch64zbc;
         "arch64zbs":     if (P.ZBS_SUPPORTED)     tests = arch64zbs;
+        "arch64zicboz":  if (P.ZICBOZ_SUPPORTED)  tests = arch64zicboz;
+        "arch64zcb":     if (P.ZCB_SUPPORTED)     tests = arch64zcb;
       endcase 
     end else begin // RV32
       case (TEST)
@@ -137,9 +139,9 @@ module testbench;
         "arch32a":      if (P.A_SUPPORTED)        tests = arch32a;
         "arch32f":      if (P.F_SUPPORTED)        tests = arch32f;
         "arch32d":      if (P.D_SUPPORTED)        tests = arch32d;
-        "arch32f_fma":      if (P.F_SUPPORTED)    tests = arch32f_fma;
-        "arch32d_fma":      if (P.D_SUPPORTED)    tests = arch32d_fma;
-        "arch32zi":     if (P.ZIFENCEI_SUPPORTED) tests = arch32zi;
+        "arch32f_fma":  if (P.F_SUPPORTED)        tests = arch32f_fma;
+        "arch32d_fma":  if (P.D_SUPPORTED)        tests = arch32d_fma;
+        "arch32zifencei":     if (P.ZIFENCEI_SUPPORTED) tests = arch32zifencei;
         "imperas32i":                             tests = imperas32i;
         "imperas32f":   if (P.F_SUPPORTED)        tests = imperas32f;
         "imperas32m":   if (P.M_SUPPORTED)        tests = imperas32m;
@@ -155,6 +157,8 @@ module testbench;
         "arch32zbb":     if (P.ZBB_SUPPORTED)     tests = arch32zbb;
         "arch32zbc":     if (P.ZBC_SUPPORTED)     tests = arch32zbc;
         "arch32zbs":     if (P.ZBS_SUPPORTED)     tests = arch32zbs;
+        "arch32zicboz":  if (P.ZICBOZ_SUPPORTED)  tests = arch32zicboz;
+        "arch32zcb":     if (P.ZCB_SUPPORTED)     tests = arch32zcb;
       endcase
     end
     if (tests.size() == 0) begin
diff --git a/testbench/tests.vh b/testbench/tests.vh
index 1637984ab..3d2d85398 100644
--- a/testbench/tests.vh
+++ b/testbench/tests.vh
@@ -44,9 +44,9 @@ string tvpaths[] = '{
 
   string coverage64gc[] = '{
     `COVERAGE,
-    "tlbNAPOT",
-    "priv",
     "ieu",
+//    "tlbNAPOT",
+    "priv",
     "ebu",
     "csrwrites",
     "ifu",
@@ -898,7 +898,7 @@ string imperas32f[] = '{
  -----/\----- EXCLUDED -----/\----- */
     };
 
-  string arch64zi[] = '{
+  string arch64zifencei[] = '{
     `RISCVARCHTEST,
     "rv64i_m/Zifencei/src/Fencei.S"
     };
@@ -917,7 +917,7 @@ string imperas32f[] = '{
     };
 
 
-  string arch32zi[] = '{
+  string arch32zifencei[] = '{
     `RISCVARCHTEST,
     "rv32i_m/Zifencei/src/Fencei.S"
     };
@@ -1481,6 +1481,49 @@ string imperas32f[] = '{
     "rv64i_m/D/src/fssub.d_b8-01.S"
 };
 
+string arch64zicboz[] = '{ // as of 12/17/23 presently cbo.zero is the only CMO insturction with riscv-arch-test support
+      `RISCVARCHTEST,
+      "rv64i_m/CMO/src/cbo.zero-01.S"
+  };
+
+string arch32zicboz[] = '{ // as of 12/17/23 presently cbo.zero is the only CMO insturction with riscv-arch-test support
+      `RISCVARCHTEST,
+      "rv32i_m/CMO/src/cbo.zero-01.S"
+  };
+
+string arch64zcb[] = '{
+      `RISCVARCHTEST,
+      "rv64i_m/C/src/clbu-01.S",
+      "rv64i_m/C/src/clh-01.S",
+      "rv64i_m/C/src/clhu-01.S",
+      "rv64i_m/C/src/clbu-01.S",
+      "rv64i_m/C/src/csb-01.S",
+      "rv64i_m/C/src/csh-01.S",
+      "rv64i_m/C/src/csext.b-01.S",
+      "rv64i_m/C/src/csext.h-01.S",
+      "rv64i_m/C/src/czext.b-01.S",
+      "rv64i_m/C/src/czext.h-01.S",
+      "rv64i_m/C/src/cmul-01.S",
+      "rv64i_m/C/src/cnot-01.S",
+      "rv64i_m/C/src/czext.w-01.S"
+  };
+
+string arch32zcb[] = '{
+      `RISCVARCHTEST,
+      "rv32i_m/C/src/clbu-01.S",
+      "rv32i_m/C/src/clh-01.S",
+      "rv32i_m/C/src/clhu-01.S",
+      "rv32i_m/C/src/clbu-01.S",
+      "rv32i_m/C/src/csb-01.S",
+      "rv32i_m/C/src/csh-01.S",
+      "rv32i_m/C/src/csext.b-01.S",
+      "rv32i_m/C/src/csext.h-01.S",
+      "rv32i_m/C/src/czext.b-01.S",
+      "rv32i_m/C/src/czext.h-01.S",
+      "rv32i_m/C/src/cmul-01.S",
+      "rv32i_m/C/src/cnot-01.S"
+  };
+
 string arch64zba[] = '{
       `RISCVARCHTEST,
       "rv64i_m/B/src/slli.uw-01.S",