From ddc56d8cd7d5d08f3dd216f05d9b4ff65cfca185 Mon Sep 17 00:00:00 2001 From: Noah Boorstin Date: Wed, 31 Mar 2021 13:41:40 -0400 Subject: [PATCH 1/2] busybear: clean up questa warnings --- wally-pipelined/regression/wally-busybear-batch.do | 2 +- wally-pipelined/regression/wally-busybear.do | 2 +- wally-pipelined/testbench/testbench-busybear.sv | 3 +-- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/wally-pipelined/regression/wally-busybear-batch.do b/wally-pipelined/regression/wally-busybear-batch.do index 036fed326..30fea8fc0 100644 --- a/wally-pipelined/regression/wally-busybear-batch.do +++ b/wally-pipelined/regression/wally-busybear-batch.do @@ -26,7 +26,7 @@ vlib work-busybear # suppress spurious warnngs about # "Extra checking for conflicts with always_comb done at vopt time" # because vsim will run vopt -vlog +incdir+../config/busybear ../testbench/*.sv ../src/*/*.sv -suppress 2583 +vlog +incdir+../config/busybear ../testbench/testbench-busybear.sv ../src/*/*.sv -suppress 2583 # start and run simulation diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do index b704aba98..24fa877de 100644 --- a/wally-pipelined/regression/wally-busybear.do +++ b/wally-pipelined/regression/wally-busybear.do @@ -26,7 +26,7 @@ vlib work-busybear # suppress spurious warnngs about # "Extra checking for conflicts with always_comb done at vopt time" # because vsim will run vopt -vlog +incdir+../config/busybear ../testbench/*.sv ../src/*/*.sv -suppress 2583 +vlog +incdir+../config/busybear ../testbench/testbench-busybear.sv ../src/*/*.sv -suppress 2583 # start and run simulation diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv index 8a75eb81f..acd883b47 100644 --- a/wally-pipelined/testbench/testbench-busybear.sv +++ b/wally-pipelined/testbench/testbench-busybear.sv @@ -145,7 +145,7 @@ module testbench_busybear(); integer regNumExpected; logic [`XLEN-1:0] PCW; - flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, dut.hart.ifu.PCM, PCW); + flopenr #(`XLEN) PCWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW); genvar i; generate @@ -484,7 +484,6 @@ module testbench_busybear(); // Track names of instructions string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; logic [31:0] InstrW; - flopenr #(32) InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW); instrNameDecTB dec(dut.hart.ifu.ic.InstrF, InstrFName); instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, From 6aed8eaea10dd6180121c3b05b59b5fbcbcd13ee Mon Sep 17 00:00:00 2001 From: Teo Ene Date: Wed, 31 Mar 2021 20:39:02 -0500 Subject: [PATCH 2/2] Updated MISA in coremark_bare config file --- wally-pipelined/config/coremark_bare/wally-config.vh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/config/coremark_bare/wally-config.vh b/wally-pipelined/config/coremark_bare/wally-config.vh index 368ae2d24..a5e3f097a 100644 --- a/wally-pipelined/config/coremark_bare/wally-config.vh +++ b/wally-pipelined/config/coremark_bare/wally-config.vh @@ -28,7 +28,7 @@ `define XLEN 64 //`define MISA (32'h00000104) -`define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12) +`define MISA (32'h00001104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12 | 1 << 0) `define A_SUPPORTED ((`MISA >> 0) % 2 == 1) `define C_SUPPORTED ((`MISA >> 2) % 2 == 1) `define D_SUPPORTED ((`MISA >> 3) % 2 == 1)