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	Fixed bug in the btb branch logging.
We were only logging branch instructions not all control flow instructions which dramatically skewed the results for sim_bp.
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				@ -213,26 +213,41 @@ module loggers import cvw::*; #(parameter cvw_t P,
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  if (P.BPRED_SUPPORTED) begin : BranchLogger
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					  if (P.BPRED_SUPPORTED) begin : BranchLogger
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    if (BPRED_LOGGER) begin
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					    if (BPRED_LOGGER) begin
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      string direction;
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					      string direction;
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      int    file;
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					      int    file, CFIfile;
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      logic  PCSrcM;
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					      logic  PCSrcM;
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      string LogFile;
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					      string LogFile, CFILogFile;
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      logic  resetD, resetEdge;
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					      logic  resetD, resetEdge;
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      flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.PCSrcE, PCSrcM);
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					      flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.PCSrcE, PCSrcM);
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      flop #(1) ResetDReg(clk, reset, resetD);
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					      flop #(1) ResetDReg(clk, reset, resetD);
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      assign resetEdge = ~reset & resetD;
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					      assign resetEdge = ~reset & resetD;
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      initial begin
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					      initial begin
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        LogFile = "branch.log"; // will break some of Ross's research analysis scripts
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					        LogFile = "branch.log"; // will break some of Ross's research analysis scripts
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					        CFILogFile = "cfi.log"; // will break some of Ross's research analysis scripts
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        //LogFile = $psprintf("branch_%s%0d.log", P.BPRED_TYPE, P.BPRED_SIZE);
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					        //LogFile = $psprintf("branch_%s%0d.log", P.BPRED_TYPE, P.BPRED_SIZE);
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        file = $fopen(LogFile, "w");
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					        file = $fopen(LogFile, "w");
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					        CFIfile = $fopen(CFILogFile, "w");
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      end
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					      end
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      always @(posedge clk) begin
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					      always @(posedge clk) begin
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        if(resetEdge) $fwrite(file, "TRAIN\n");
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					        if(resetEdge) begin 
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        if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename);
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					          $fwrite(file, "TRAIN\n");
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					          $fwrite(CFIfile, "TRAIN\n");
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					        end
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					        if(StartSample) begin
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					          $fwrite(file, "BEGIN %s\n", memfilename);
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					          $fwrite(CFIfile, "BEGIN %s\n", memfilename);
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					        end
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        if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
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					        if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
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          direction = PCSrcM ? "t" : "n";
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					          direction = PCSrcM ? "t" : "n";
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          $fwrite(file, "%h %s\n", dut.core.PCM, direction);
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					          $fwrite(file, "%h %s\n", dut.core.PCM, direction);
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        end
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					        end
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        if(EndSample) $fwrite(file, "END %s\n", memfilename);
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					        if((|dut.core.ifu.InstrClassM) & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
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					          direction = PCSrcM ? "t" : "n";
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					          $fwrite(CFIfile, "%h %s\n", dut.core.PCM, direction);
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					        end
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					        if(EndSample) begin
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					          $fwrite(file, "END %s\n", memfilename);
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					          $fwrite(CFIfile, "END %s\n", memfilename);
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					        end
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      end
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					      end
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    end
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					    end
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  end
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					  end
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