diff --git a/fpga/generator/wave_config.wcfg b/fpga/generator/wave_config.wcfg
index 413d5cdeb..833e2fbc8 100644
--- a/fpga/generator/wave_config.wcfg
+++ b/fpga/generator/wave_config.wcfg
@@ -9,15 +9,15 @@
-
-
-
+
+
+
-
-
+
+
-
+
@@ -53,6 +53,7 @@
CPU to LSU
label
+
FullPathName
wallypipelinedsoc/core/IEUAdrM[63:0]
@@ -81,7 +82,6 @@
xIP
label
-
FullPathName
wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW_5[9:9]
@@ -91,46 +91,36 @@
STYLE_DIGITAL
+
+ FullPathName
+ wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW_5[9:9]
+ MIP_REGW_5[9:9]
+ HEXRADIX
+ true
+ STYLE_DIGITAL
+
PLIC
label
-
- FullPathName
- wallypipelinedsoc/uncore/plic.plic/requests[12:1]
- requests[12:1]
- HEXRADIX
- true
- STYLE_DIGITAL
-
-
- FullPathName
- wallypipelinedsoc/uncore/plic.plic/intPending[12:1]
- intPending[12:1]
- HEXRADIX
- true
- STYLE_DIGITAL
-
-
- FullPathName
- wallypipelinedsoc/uncore/plic.plic/intInProgress[12:1]
- intInProgress[12:1]
- HEXRADIX
- true
- STYLE_DIGITAL
-
interrupts
label
+ FullPathName
wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0]
MEDELEG_REGW[63:0]
HEXRADIX
+ true
+ STYLE_DIGITAL
+ FullPathName
wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11:0]
MIDELEG_REGW[11:0]
HEXRADIX
+ true
+ STYLE_DIGITAL
FullPathName
@@ -143,58 +133,56 @@
LSU to Bus
label
-
- FullPathName
- wallypipelinedsoc/core/lsu/LSUBusRead
- LSUBusRead
- true
- STYLE_DIGITAL
-
-
- FullPathName
- wallypipelinedsoc/core/lsu/LSUBusWrite
- LSUBusWrite
- true
- STYLE_DIGITAL
-
-
- FullPathName
- wallypipelinedsoc/core/lsu/LSUBusAdr[31:0]
- LSUBusAdr[31:0]
+
+ wallypipelinedsoc/core/lsu/LSUHADDR[31:0]
+ LSUHADDR[31:0]
HEXRADIX
- true
- STYLE_DIGITAL
-
- FullPathName
- wallypipelinedsoc/core/lsu/LSUBusSize[1:0]
- LSUBusSize[1:0]
+
+ wallypipelinedsoc/core/lsu/LSUHBURST[2:0]
+ LSUHBURST[2:0]
HEXRADIX
- true
- STYLE_DIGITAL
-
- FullPathName
- wallypipelinedsoc/core/lsu/LSUBusHWDATA[63:0]
- LSUBusHWDATA[63:0]
+
+ wallypipelinedsoc/core/lsu/LSUHREADY
+ LSUHREADY
+
+
+ wallypipelinedsoc/core/lsu/LSUHSIZE[1:0]
+ LSUHSIZE[1:0]
HEXRADIX
- true
- STYLE_DIGITAL
-
- FullPathName
- wallypipelinedsoc/core/lsu/LSUBusHRDATA[63:0]
- LSUBusHRDATA[63:0]
+
+ wallypipelinedsoc/core/lsu/LSUHWDATA[63:0]
+ LSUHWDATA[63:0]
HEXRADIX
- true
- STYLE_DIGITAL
-
- FullPathName
- wallypipelinedsoc/core/lsu/LSUBusAck
- LSUBusAck
- true
- STYLE_DIGITAL
+
+ wallypipelinedsoc/core/lsu/LSUHWRITE
+ LSUHWRITE
+
+
+
+ IFU to Bus
+ label
+
+ wallypipelinedsoc/core/ifu/IFUHADDR[31:0]
+ IFUHADDR[31:0]
+ HEXRADIX
+
+
+ wallypipelinedsoc/core/ifu/IFUHREADY
+ IFUHREADY
+
+
+ wallypipelinedsoc/core/ifu/IFUHTRANS[0:0]
+ IFUHTRANS[0:0]
+ HEXRADIX
+
+
+ wallypipelinedsoc/core/ifu/IFUHTRANS_1[0:0]
+ IFUHTRANS_1[0:0]
+ HEXRADIX
@@ -252,43 +240,74 @@
sdc
label
-
+
+
+ dcache
+ label
+
+
FullPathName
- wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_ERROR_Q
- r_DAT_ERROR_Q
- true
- STYLE_DIGITAL
-
-
- FullPathName
- wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[4:0]
- r_curr_state[4:0]
+ wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[3:0]
+ CurrState[3:0]
HEXRADIX
true
STYLE_DIGITAL
-
- FullPathName
- wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[3:0]
- r_curr_state[3:0]
- HEXRADIX
- true
- STYLE_DIGITAL
-
-
- FullPathName
- wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[3:0]
- r_curr_state[3:0]
- HEXRADIX
- true
- STYLE_DIGITAL
-
-
- FullPathName
- wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_CRC16
- i_ERROR_CRC16
- true
- STYLE_DIGITAL
-
+
+
+ EBU
+ label
+
+ wallypipelinedsoc/core/ebu.ebu/HADDR[31:0]
+ HADDR[31:0]
+ HEXRADIX
+
+
+ wallypipelinedsoc/core/ebu.ebu/HBURST[2:0]
+ HBURST[2:0]
+ HEXRADIX
+
+
+ wallypipelinedsoc/core/ebu.ebu/HPROT[3:0]
+ HPROT[3:0]
+ HEXRADIX
+
+
+ wallypipelinedsoc/core/ebu.ebu/HREADY
+ HREADY
+
+
+ wallypipelinedsoc/core/ebu.ebu/HRESP
+ HRESP
+
+
+ wallypipelinedsoc/core/ebu.ebu/HSIZE[2:0]
+ HSIZE[2:0]
+ HEXRADIX
+
+
+ wallypipelinedsoc/core/ebu.ebu/HTRANS[1:0]
+ HTRANS[1:0]
+ HEXRADIX
+
+
+ wallypipelinedsoc/core/ebu.ebu/HTRANS_1[1:0]
+ HTRANS_1[1:0]
+ HEXRADIX
+
+
+ wallypipelinedsoc/core/ebu.ebu/HWDATA[63:0]
+ HWDATA[63:0]
+ HEXRADIX
+
+
+ wallypipelinedsoc/core/ebu.ebu/HWRITE
+ HWRITE
+
+
+ wallypipelinedsoc/core/HRDATA[63:0]
+ HRDATA[63:0]
+ HEXRADIX
+
diff --git a/pipelined/src/generic/mem/brom1p1r.sv b/pipelined/src/generic/mem/brom1p1r.sv
index 9bad5c6d7..ef58f9254 100644
--- a/pipelined/src/generic/mem/brom1p1r.sv
+++ b/pipelined/src/generic/mem/brom1p1r.sv
@@ -53,49 +53,49 @@ module brom1p1r
if(PRELOAD_ENABLED) begin
initial begin
- RAM[0] = 64'h9581819300002197;
- RAM[1] = 64'h4281420141014081;
- RAM[2] = 64'h4481440143814301;
- RAM[3] = 64'h4681460145814501;
- RAM[4] = 64'h4881480147814701;
- RAM[5] = 64'h4a814a0149814901;
- RAM[6] = 64'h4c814c014b814b01;
- RAM[7] = 64'h4e814e014d814d01;
- RAM[8] = 64'h0110011b4f814f01;
- RAM[9] = 64'h059b45011161016e;
- RAM[10] = 64'h0004063705fe0010;
- RAM[11] = 64'h05a000ef8006061b;
- RAM[12] = 64'h0ff003930000100f;
- RAM[13] = 64'h4e952e3110060e37;
- RAM[14] = 64'hc602829b0053f2b7;
- RAM[15] = 64'h2023fe02dfe312fd;
- RAM[16] = 64'h829b0053f2b7007e;
- RAM[17] = 64'hfe02dfe312fdc602;
- RAM[18] = 64'h4de31efd000e2023;
- RAM[19] = 64'h059bf1402573fdd0;
- RAM[20] = 64'h0000061705e20870;
- RAM[21] = 64'h0010029b01260613;
- RAM[22] = 64'h11010002806702fe;
- RAM[23] = 64'h84b2842ae426e822;
- RAM[24] = 64'h892ee04aec064511;
- RAM[25] = 64'h06e000ef07e000ef;
- RAM[26] = 64'h979334fd02905563;
- RAM[27] = 64'h07930177d4930204;
- RAM[28] = 64'h4089093394be2004;
- RAM[29] = 64'h04138522008905b3;
- RAM[30] = 64'h19e3014000ef2004;
- RAM[31] = 64'h64a2644260e2fe94;
- RAM[32] = 64'h6749808261056902;
- RAM[33] = 64'hdfed8b8510472783;
- RAM[34] = 64'h2423479110a73823;
- RAM[35] = 64'h10472783674910f7;
- RAM[36] = 64'h20058693ffed8b89;
- RAM[37] = 64'h05a1118737836749;
- RAM[38] = 64'hfed59be3fef5bc23;
- RAM[39] = 64'h1047278367498082;
- RAM[40] = 64'h47858082dfed8b85;
- RAM[41] = 64'h40a7853b4015551b;
- RAM[42] = 64'h808210a7a02367c9;
+ ROM[0] = 64'h9581819300002197;
+ ROM[1] = 64'h4281420141014081;
+ ROM[2] = 64'h4481440143814301;
+ ROM[3] = 64'h4681460145814501;
+ ROM[4] = 64'h4881480147814701;
+ ROM[5] = 64'h4a814a0149814901;
+ ROM[6] = 64'h4c814c014b814b01;
+ ROM[7] = 64'h4e814e014d814d01;
+ ROM[8] = 64'h0110011b4f814f01;
+ ROM[9] = 64'h059b45011161016e;
+ ROM[10] = 64'h0004063705fe0010;
+ ROM[11] = 64'h05a000ef8006061b;
+ ROM[12] = 64'h0ff003930000100f;
+ ROM[13] = 64'h4e952e3110060e37;
+ ROM[14] = 64'hc602829b0053f2b7;
+ ROM[15] = 64'h2023fe02dfe312fd;
+ ROM[16] = 64'h829b0053f2b7007e;
+ ROM[17] = 64'hfe02dfe312fdc602;
+ ROM[18] = 64'h4de31efd000e2023;
+ ROM[19] = 64'h059bf1402573fdd0;
+ ROM[20] = 64'h0000061705e20870;
+ ROM[21] = 64'h0010029b01260613;
+ ROM[22] = 64'h11010002806702fe;
+ ROM[23] = 64'h84b2842ae426e822;
+ ROM[24] = 64'h892ee04aec064511;
+ ROM[25] = 64'h06e000ef07e000ef;
+ ROM[26] = 64'h979334fd02905563;
+ ROM[27] = 64'h07930177d4930204;
+ ROM[28] = 64'h4089093394be2004;
+ ROM[29] = 64'h04138522008905b3;
+ ROM[30] = 64'h19e3014000ef2004;
+ ROM[31] = 64'h64a2644260e2fe94;
+ ROM[32] = 64'h6749808261056902;
+ ROM[33] = 64'hdfed8b8510472783;
+ ROM[34] = 64'h2423479110a73823;
+ ROM[35] = 64'h10472783674910f7;
+ ROM[36] = 64'h20058693ffed8b89;
+ ROM[37] = 64'h05a1118737836749;
+ ROM[38] = 64'hfed59be3fef5bc23;
+ ROM[39] = 64'h1047278367498082;
+ ROM[40] = 64'h47858082dfed8b85;
+ ROM[41] = 64'h40a7853b4015551b;
+ ROM[42] = 64'h808210a7a02367c9;
end
end