From 5d12afa6718993e1b0ed416557f4b52beed0de42 Mon Sep 17 00:00:00 2001
From: Limnanthes Serafini <lserafini@hmc.edu>
Date: Thu, 13 Apr 2023 21:01:57 -0700
Subject: [PATCH] Some cleanup

---
 src/cache/cache.sv            | 18 +++++++++---------
 src/cache/cacheLRU.sv         |  4 ++--
 src/cache/cachefsm.sv         |  4 ++--
 src/cache/subcachelineread.sv |  5 ++---
 4 files changed, 15 insertions(+), 16 deletions(-)

diff --git a/src/cache/cache.sv b/src/cache/cache.sv
index 4721eb167..ebee8f4f1 100644
--- a/src/cache/cache.sv
+++ b/src/cache/cache.sv
@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// cache 
+// cache.sv
 //
 // Written: Ross Thompson ross1728@gmail.com
 // Created: 7 July 2021
@@ -167,22 +167,22 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
     // Adjust byte mask from word to cache line
     onehotdecoder #(LOGCWPL) adrdec(.bin(PAdr[LOGCWPL+LOGLLENBYTES-1:LOGLLENBYTES]), .decoded(MemPAdrDecoded));
     for(index = 0; index < 2**LOGCWPL; index++) begin
-       assign DemuxedByteMask[(index+1)*(WORDLEN/8)-1:index*(WORDLEN/8)] = MemPAdrDecoded[index] ? ByteMask : '0;
+      assign DemuxedByteMask[(index+1)*(WORDLEN/8)-1:index*(WORDLEN/8)] = MemPAdrDecoded[index] ? ByteMask : '0;
     end
     assign FetchBufferByteSel = SetValid & ~SetDirty ? '1 : ~DemuxedByteMask;  // If load miss set all muxes to 1.
 
     // Merge write data into fetched cache line for store miss
     for(index = 0; index < LINELEN/8; index++) begin
-       mux2 #(8) WriteDataMux(.d0(CacheWriteData[(8*index)%WORDLEN+7:(8*index)%WORDLEN]),
-         .d1(FetchBuffer[8*index+7:8*index]), .s(FetchBufferByteSel[index]), .y(LineWriteData[8*index+7:8*index]));
+      mux2 #(8) WriteDataMux(.d0(CacheWriteData[(8*index)%WORDLEN+7:(8*index)%WORDLEN]),
+        .d1(FetchBuffer[8*index+7:8*index]), .s(FetchBufferByteSel[index]), .y(LineWriteData[8*index+7:8*index]));
     end
     assign LineByteMask = SetValid ? '1 : SetDirty ? DemuxedByteMask : '0;
   end
   else
     begin:WriteSelLogic
-       // No need for this mux if the cache does not handle writes.
-       assign LineWriteData = FetchBuffer;
-       assign LineByteMask = '1;
+      // No need for this mux if the cache does not handle writes.
+      assign LineWriteData = FetchBuffer;
+      assign LineByteMask = '1;
     end
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Flush logic
@@ -203,8 +203,8 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
     assign FlushWayFlag = FlushWay[NUMWAYS-1];
   end // block: flushlogic
   else begin:flushlogic
-     assign FlushWayFlag = 0;
-     assign FlushAdrFlag = 0;
+    assign FlushWayFlag = 0;
+    assign FlushAdrFlag = 0;
   end
    
   /////////////////////////////////////////////////////////////////////////////////////////////
diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv
index 1e7101365..87d9f072a 100644
--- a/src/cache/cacheLRU.sv
+++ b/src/cache/cacheLRU.sv
@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// dcache (data cache)
+// cacheLRU.sv
 //
 // Written: Ross Thompson ross1728@gmail.com
 // Created: 20 July 2021
@@ -37,7 +37,7 @@ module cacheLRU
   input  logic                CacheEn,         // Enable the cache memory arrays.  Disable hold read data constant
   input  logic [NUMWAYS-1:0]  HitWay,          // Which way is valid and matches PAdr's tag
   input  logic [NUMWAYS-1:0]  ValidWay,        // Which ways for a particular set are valid, ignores tag
-  input  logic [SETLEN-1:0]   CacheSet,            // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
+  input  logic [SETLEN-1:0]   CacheSet,        // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
   input  logic [SETLEN-1:0]   PAdr,            // Physical address 
   input  logic                LRUWriteEn,      // Update the LRU state
   input  logic                SetValid,        // Set the dirty bit in the selected way and set
diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv
index 2a5cb8235..525d7524f 100644
--- a/src/cache/cachefsm.sv
+++ b/src/cache/cachefsm.sv
@@ -1,11 +1,11 @@
 ///////////////////////////////////////////
-// dcache (data cache) fsm
+// cachefsm.sv
 //
 // Written: Ross Thompson ross1728@gmail.com
 // Created: 25 August 2021
 // Modified: 20 January 2023
 //
-// Purpose: Controller for the dcache fsm
+// Purpose: Controller for the cache fsm
 //
 // Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.14 and Table 7.1)
 //
diff --git a/src/cache/subcachelineread.sv b/src/cache/subcachelineread.sv
index 58d022a71..ea305fb6c 100644
--- a/src/cache/subcachelineread.sv
+++ b/src/cache/subcachelineread.sv
@@ -1,11 +1,11 @@
 ///////////////////////////////////////////
-// subcachelineread
+// subcachelineread.sv
 //
 // Written: Ross Thompson ross1728@gmail.com
 // Created: 4 February 2022
 // Modified: 20 January 2023
 //
-// Purpose: Muxes the cache line downto the word size.  Also include possilbe save/restore registers/muxes.
+// Purpose: Muxes the cache line down to the word size.  Also include possible save/restore registers/muxes.
 //
 // Documentation: RISC-V System on Chip Design Chapter 7
 
@@ -31,7 +31,6 @@
 
 module subcachelineread #(parameter LINELEN, WORDLEN, 
   parameter MUXINTERVAL )(     // The number of bits between mux. Set to 16 for I$ to support compressed.  Set to `LLEN for D$
-
   input  logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr,       // Physical address 
   input  logic [LINELEN-1:0]                     ReadDataLine,// Read data of the whole cacheline
   output logic [WORDLEN-1:0]                     ReadDataWord // read data of selected word.