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Merged in the debug ila updates.

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This commit is contained in:
Ross Thompson 2022-01-18 17:29:21 -06:00
parent 2508b9d35a
commit 5cf686429d
7 changed files with 33 additions and 6 deletions
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27
fpga/constraints/debug2.xdc
View File

@ -591,3 +591,30 @@ create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe126] set_property port_width 3 [get_debug_ports u_ila_0/probe126]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe126] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe126]
connect_debug_port u_ila_0/probe126 [get_nets [list {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[0]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[1]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[2]} ]] connect_debug_port u_ila_0/probe126 [get_nets [list {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[0]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[1]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[2]} ]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe127]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe127]
connect_debug_port u_ila_0/probe127 [get_nets [list {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[0]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[1]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[2]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[3]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[4]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[5]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[6]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[7]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[8]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[9]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[10]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[11]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[12]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[13]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[14]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[15]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[16]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[17]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[18]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[19]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[20]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[21]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[22]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[23]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[24]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[25]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[26]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[27]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[28]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[29]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[30]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[31]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[32]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[33]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[34]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[35]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[36]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[37]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[38]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[39]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[40]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[41]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[42]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[43]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[44]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[45]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[46]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[47]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[48]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[49]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[50]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[51]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[52]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[53]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[54]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[55]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[56]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[57]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[58]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[59]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[60]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[61]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[62]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe128]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe128]
connect_debug_port u_ila_0/probe128 [get_nets [list {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[0]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[1]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[2]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[3]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[4]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[5]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[6]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[7]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[8]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[9]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[10]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[11]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[12]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[13]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[14]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[15]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[16]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[17]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[18]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[19]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[20]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[21]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[22]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[23]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[24]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[25]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[26]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[27]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[28]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[29]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[30]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[31]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[32]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[33]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[34]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[35]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[36]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[37]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[38]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[39]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[40]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[41]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[42]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[43]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[44]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[45]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[46]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[47]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[48]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[49]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[50]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[51]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[52]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[53]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[54]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[55]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[56]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[57]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[58]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[59]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[60]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[61]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[62]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe129]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe129]
connect_debug_port u_ila_0/probe129 [get_nets [list {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[0]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[1]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[2]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[3]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[4]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[5]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[6]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[7]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[8]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[9]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[10]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[11]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[12]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[13]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[14]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[15]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[16]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[17]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[18]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[19]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[20]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[21]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[22]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[23]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[24]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[25]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[26]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[27]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[28]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[29]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[30]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[31]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[32]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[33]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[34]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[35]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[36]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[37]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[38]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[39]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[40]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[41]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[42]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[43]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[44]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[45]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[46]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[47]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[48]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[49]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[50]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[51]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[52]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[53]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[54]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[55]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[56]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[57]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[58]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[59]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[60]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[61]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[62]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe130]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe130]
connect_debug_port u_ila_0/probe130 [get_nets [list wallypipelinedsoc/hart/ieu/dp/RegWriteW]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe131]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe131]
connect_debug_port u_ila_0/probe131 [get_nets [list {wallypipelinedsoc/hart/priv.priv/CSRWriteM} ]]

2
pipelined/src/ieu/datapath.sv
View File

@ -58,7 +58,7 @@ module datapath (
output logic [`XLEN-1:0] WriteDataM, output logic [`XLEN-1:0] WriteDataM,
// Writeback stage signals // Writeback stage signals
input logic StallW, FlushW, input logic StallW, FlushW,
input logic RegWriteW, (* mark_debug = "true" *) input logic RegWriteW,
input logic SquashSCW, input logic SquashSCW,
input logic [2:0] ResultSrcW, input logic [2:0] ResultSrcW,
output logic [`XLEN-1:0] ReadDataW, output logic [`XLEN-1:0] ReadDataW,

2
pipelined/src/ieu/regfile.sv
View File

@ -39,7 +39,7 @@ module regfile (
localparam NUMREGS = `E_SUPPORTED ? 16 : 32; // only 16 registers in E mode localparam NUMREGS = `E_SUPPORTED ? 16 : 32; // only 16 registers in E mode
logic [`XLEN-1:0] rf[NUMREGS-1:1]; (* mark_debug = "true" *) logic [`XLEN-1:0] rf[NUMREGS-1:1];
integer i; integer i;
// three ported register file // three ported register file

2
pipelined/src/privileged/csr.sv
View File

@ -79,7 +79,7 @@ module csr #(parameter
logic [`XLEN-1:0] CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRNReadValM, CSRCReadValM, CSRReadValM; logic [`XLEN-1:0] CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRNReadValM, CSRCReadValM, CSRReadValM;
logic [`XLEN-1:0] CSRSrcM, CSRRWM, CSRRSM, CSRRCM, CSRWriteValM; logic [`XLEN-1:0] CSRSrcM, CSRRWM, CSRRSM, CSRRCM, CSRWriteValM;
logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, USTATUS_REGW; (* mark_debug = "true" *) logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, USTATUS_REGW;
logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW; logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW;
logic WriteMSTATUSM, WriteSSTATUSM, WriteUSTATUSM; logic WriteMSTATUSM, WriteSSTATUSM, WriteUSTATUSM;
logic CSRMWriteM, CSRSWriteM, CSRUWriteM; logic CSRMWriteM, CSRSWriteM, CSRUWriteM;

2
pipelined/src/privileged/csrm.sv
View File

@ -89,7 +89,7 @@ module csrm #(parameter
); );
logic [`XLEN-1:0] MISA_REGW, MHARTID_REGW; logic [`XLEN-1:0] MISA_REGW, MHARTID_REGW;
logic [`XLEN-1:0] MSCRATCH_REGW; (* mark_debug = "true" *) logic [`XLEN-1:0] MSCRATCH_REGW;
(* mark_debug = "true" *) logic [`XLEN-1:0] MCAUSE_REGW, MTVAL_REGW; (* mark_debug = "true" *) logic [`XLEN-1:0] MCAUSE_REGW, MTVAL_REGW;
logic WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM; logic WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM;
logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM; logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM;

2
pipelined/src/privileged/csrs.sv
View File

@ -78,7 +78,7 @@ module csrs #(parameter
logic WriteSTVECM; logic WriteSTVECM;
logic WriteSSCRATCHM, WriteSEPCM; logic WriteSSCRATCHM, WriteSEPCM;
logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM; logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM;
logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW; (* mark_debug = "true" *) logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW;
(* mark_debug = "true" *) logic [`XLEN-1:0] SCAUSE_REGW; (* mark_debug = "true" *) logic [`XLEN-1:0] SCAUSE_REGW;
logic InstrValidNotFlushedM; logic InstrValidNotFlushedM;

2
pipelined/src/privileged/privileged.sv
View File

@ -31,7 +31,7 @@
module privileged ( module privileged (
input logic clk, reset, input logic clk, reset,
input logic FlushD, FlushE, FlushM, FlushW, StallD, StallE, StallM, StallW, input logic FlushD, FlushE, FlushM, FlushW, StallD, StallE, StallM, StallW,
input logic CSRReadM, CSRWriteM, (* mark_debug = "true" *) input logic CSRReadM, CSRWriteM,
input logic [`XLEN-1:0] SrcAM, input logic [`XLEN-1:0] SrcAM,
input logic [`XLEN-1:0] PCM, input logic [`XLEN-1:0] PCM,
input logic [31:0] InstrM, input logic [31:0] InstrM,