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Updated arty a7 fpga top.
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@ -225,7 +225,7 @@ module fpgaTop
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.peripheral_aresetn(peripheral_aresetn));
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.peripheral_aresetn(peripheral_aresetn));
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// wally
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// wally
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wallypipelinedsoc wallypipelinedsoc
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wallypipelinedsocwrapper wallypipelinedsocwrapper
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(.clk(CPUCLK),
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(.clk(CPUCLK),
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.reset_ext(bus_struct_reset),
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.reset_ext(bus_struct_reset),
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// bus interface
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// bus interface
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