mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Updated the ptw, lsuarb and dcache to hopefully solve the interlock issues.
This commit is contained in:
Ross Thompson
parent
f01be12162
commit
5ca7dc619c
59
wally-pipelined/src/cache/dcache.sv
vendored
59
wally-pipelined/src/cache/dcache.sv
vendored
@ -53,6 +53,7 @@ module dcache
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input logic DTLBMissM,
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input logic CacheableM,
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input logic DTLBWriteM,
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input logic SelPTW,
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// ahb side
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output logic [`PA_BITS-1:0] AHBPAdr, // to ahb
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output logic AHBRead,
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@ -443,7 +444,13 @@ module dcache
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// The page table walker asserts it's control 1 cycle
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// after the TLBs miss.
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DCacheStall = 1'b1;
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NextState = STATE_READY;
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end
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else if(SelPTW) begin
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// Now we have activated the ptw.
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// Do not assert Stall as we are now directing the stall the ptw.
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NextState = STATE_PTW_READY;
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CommittedM = 1'b1;
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end
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// amo hit
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else if(|AtomicM & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
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@ -592,7 +599,7 @@ module dcache
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// now all output connect to PTW instead of CPU.
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CommittedM = 1'b1;
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// return to ready if page table walk completed.
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if (DTLBWriteM) begin
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if (~SelPTW) begin
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NextState = STATE_PTW_ACCESS_AFTER_WALK;
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// read hit valid cached
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@ -655,57 +662,11 @@ module dcache
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end
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STATE_PTW_ACCESS_AFTER_WALK: begin
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DCacheStall = 1'b1;
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SelAdrM = 1'b1;
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// amo hit
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if(|AtomicM & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
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NextState = STATE_AMO_UPDATE;
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DCacheStall = 1'b1;
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if(StallW) NextState = STATE_CPU_BUSY;
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else NextState = STATE_AMO_UPDATE;
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end
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// read hit valid cached
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else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
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DCacheStall = 1'b0;
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if(StallW) NextState = STATE_CPU_BUSY;
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else NextState = STATE_READY;
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end
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// write hit valid cached
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else if (MemRWM[0] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
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DCacheStall = 1'b0;
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SRAMWordWriteEnableM = 1'b1;
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SetDirtyM = 1'b1;
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if(StallW) NextState = STATE_CPU_BUSY;
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else NextState = STATE_READY;
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end
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// read or write miss valid cached
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else if((|MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & ~CacheHit & ~DTLBMissM) begin
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NextState = STATE_MISS_FETCH_WDV;
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CntReset = 1'b1;
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DCacheStall = 1'b1;
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end
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// uncached write
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else if(MemRWM[0] & ~CacheableM & ~ExceptionM & ~DTLBMissM) begin
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NextState = STATE_UNCACHED_WRITE;
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CntReset = 1'b1;
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DCacheStall = 1'b1;
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AHBWrite = 1'b1;
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end
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// uncached read
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else if(MemRWM[1] & ~CacheableM & ~ExceptionM & ~DTLBMissM) begin
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NextState = STATE_UNCACHED_READ;
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CntReset = 1'b1;
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DCacheStall = 1'b1;
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AHBRead = 1'b1;
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end
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// fault
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else if(AnyCPUReqM & (ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
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CommittedM = 1'b1;
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NextState = STATE_READY;
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end
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else NextState = STATE_READY;
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end
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STATE_CPU_BUSY : begin
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CommittedM = 1'b1;
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@ -126,7 +126,6 @@ module lsu
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logic HPTWStall;
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logic [`XLEN-1:0] HPTWPAdrE;
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logic [`XLEN-1:0] HPTWPAdrM;
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logic HPTWTranslate;
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logic HPTWReadM;
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logic [1:0] MemRWMtoDCache;
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logic [2:0] Funct3MtoDCache;
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@ -170,8 +169,8 @@ module lsu
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.HPTWStall(HPTWStall),
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.HPTWPAdrE(HPTWPAdrE),
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.HPTWPAdrM(HPTWPAdrM),
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.HPTWTranslate(HPTWTranslate),
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.HPTWReadM(HPTWReadM),
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.SelPTW(SelPTW),
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.WalkerInstrPageFaultF(WalkerInstrPageFaultF),
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.WalkerLoadPageFaultM(WalkerLoadPageFaultM),
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.WalkerStorePageFaultM(WalkerStorePageFaultM));
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@ -182,7 +181,7 @@ module lsu
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lsuArb arbiter(.clk(clk),
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.reset(reset),
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// HPTW connection
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.HPTWTranslate(HPTWTranslate),
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.SelPTW(SelPTW),
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.HPTWReadM(HPTWReadM),
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.HPTWPAdrE(HPTWPAdrE),
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.HPTWPAdrM(HPTWPAdrM),
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@ -214,8 +213,9 @@ module lsu
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.ReadDataWfromDCache(ReadDataWfromDCache),
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.CommittedMfromDCache(CommittedMfromDCache),
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.PendingInterruptMtoDCache(PendingInterruptMtoDCache),
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.DCacheStall(DCacheStall),
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.SelPTW(SelPTW));
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.DCacheStall(DCacheStall));
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mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
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@ -243,7 +243,9 @@ module lsu
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// .SelRegions(DHSELRegionsM),
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.*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist?
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// *** BUG, this is most likely wrong
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assign CacheableMtoDCache = SelPTW ? 1'b1 : CacheableM;
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generate
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if (`XLEN == 32) assign DCtoAHBSizeM = CacheableMtoDCache ? 3'b010 : Funct3MtoDCache;
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else assign DCtoAHBSizeM = CacheableMtoDCache ? 3'b011 : Funct3MtoDCache;
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@ -335,6 +337,7 @@ module lsu
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.DTLBMissM(DTLBMissM),
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.CacheableM(CacheableMtoDCache),
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.DTLBWriteM(DTLBWriteM),
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.SelPTW(SelPTW),
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// AHB connection
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.AHBPAdr(DCtoAHBPAdrM),
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@ -30,7 +30,7 @@ module lsuArb
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(input logic clk, reset,
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// from page table walker
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input logic HPTWTranslate,
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input logic SelPTW,
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input logic HPTWReadM,
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input logic [`XLEN-1:0] HPTWPAdrE,
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input logic [`XLEN-1:0] HPTWPAdrM,
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@ -62,7 +62,6 @@ module lsuArb
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output logic [`XLEN-1:0] MemAdrEtoDCache,
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output logic StallWtoDCache,
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output logic PendingInterruptMtoDCache,
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output logic SelPTW,
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// from D Cache
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@ -74,72 +73,10 @@ module lsuArb
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);
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// HPTWTranslate is the request for memory by the page table walker. When
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// this is high the page table walker gains priority over the CPU's data
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// input. Note the ptw only makes a request after an instruction or data
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// tlb miss. It is entirely possible the dcache is currently processing
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// a data cache miss when an instruction tlb miss occurs. If an instruction
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// in the E stage causes a d cache miss, the d cache will immediately start
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// processing the request. Simultaneously the ITLB misses. By the time
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// the TLB miss causes the page table walker to issue the first request
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// to data memory the d cache is already busy. We can interlock by
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// leveraging Stall as a d cache busy. We will need an FSM to handle this.
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typedef enum{StateReady,
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StatePTWPending,
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StatePTWActive} statetype;
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statetype CurrState, NextState;
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logic [2:0] PTWSize;
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flopenl #(.TYPE(statetype)) StateReg(.clk(clk),
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.load(reset),
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.en(1'b1),
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.d(NextState),
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.val(StateReady),
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.q(CurrState));
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always_comb begin
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case(CurrState)
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StateReady:
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if (HPTWTranslate) NextState = StatePTWActive;
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else NextState = StateReady;
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StatePTWActive:
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if (HPTWTranslate) NextState = StatePTWActive;
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else NextState = StateReady;
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default: NextState = StateReady;
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endcase
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end
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/* -----\/----- EXCLUDED -----\/-----
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always_comb begin
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case(CurrState)
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StateReady:
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/-* -----\/----- EXCLUDED -----\/-----
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if (HPTWTranslate & DataStall) NextState = StatePTWPending;
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else
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-----/\----- EXCLUDED -----/\----- *-/
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if (HPTWTranslate) NextState = StatePTWActive;
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else NextState = StateReady;
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StatePTWPending:
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if (HPTWTranslate & ~DataStall) NextState = StatePTWActive;
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else if (HPTWTranslate & DataStall) NextState = StatePTWPending;
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else NextState = StateReady;
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StatePTWActive:
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if (HPTWTranslate) NextState = StatePTWActive;
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else NextState = StateReady;
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default: NextState = StateReady;
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endcase
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end
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-----/\----- EXCLUDED -----/\----- */
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// multiplex the outputs to LSU
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assign DisableTranslation = SelPTW; // change names between SelPTW would be confusing in DTLB.
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assign SelPTW = (CurrState == StatePTWActive && HPTWTranslate) || (CurrState == StateReady && HPTWTranslate);
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assign MemRWMtoDCache = SelPTW ? {HPTWReadM, 1'b0} : MemRWM;
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generate
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@ -49,8 +49,7 @@ module pagetablewalker
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output logic [`XLEN-1:0] PageTableEntryF, PageTableEntryM,
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output logic [1:0] PageTypeF, PageTypeM,
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output logic ITLBWriteF, DTLBWriteM,
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output logic SelPTW,
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// *** modify to send to LSU // *** KMG: These are inputs/results from the ahblite whose addresses should have already been checked, so I don't think they need to be sent through the LSU
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@ -61,7 +60,6 @@ module pagetablewalker
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// *** modify to send to LSU
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output logic [`XLEN-1:0] HPTWPAdrE, // this probalby should be `PA_BITS wide
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output logic [`XLEN-1:0] HPTWPAdrM, // this probalby should be `PA_BITS wide
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output logic HPTWTranslate, // *** rename to HPTWReq
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output logic HPTWReadM,
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@ -86,7 +84,6 @@ module pagetablewalker
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logic [`PPN_BITS-1:0] CurrentPPN;
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logic [`SVMODE_BITS-1:0] SvMode;
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logic MemStore;
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logic DTLBWriteM_d;
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// PTE Control Bits
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logic Dirty, Accessed, Global, User,
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@ -100,44 +97,34 @@ module pagetablewalker
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logic StartWalk;
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logic EndWalk;
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typedef enum {LEVEL0_WDV,
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typedef enum {LEVEL0_SET_ADRE,
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LEVEL0_WDV,
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LEVEL0,
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LEVEL1_SET_ADRE,
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LEVEL1_WDV,
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LEVEL1,
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LEVEL2_SET_ADRE,
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LEVEL2_WDV,
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LEVEL2,
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LEVEL3_SET_ADRE,
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LEVEL3_WDV,
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LEVEL3,
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LEAF,
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IDLE,
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START,
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FAULT} statetype;
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statetype WalkerState, NextWalkerState;
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statetype WalkerState, NextWalkerState, PreviousWalkerState;
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logic PRegEn;
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logic SelDataTranslation;
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logic AnyTLBMissM;
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flop #(`XLEN) HPTWPAdrMReg(.clk(clk),
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.d(HPTWPAdrE),
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.q(HPTWPAdrM));
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flop #(2) PageTypeReg(.clk(clk),
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.d(PageType),
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.q(PageTypeM));
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flop #(`XLEN) PageTableEntryReg(.clk(clk),
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.d(PageTableEntry),
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.q(PageTableEntryM));
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flop #(1) DTLBWriteReg(.clk(clk),
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.d(DTLBWriteM_d),
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.q(DTLBWriteM));
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flop #(1) HPTWReadMReg(.clk(clk),
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.d(HPTWReadE),
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.q(HPTWReadM));
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assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
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@ -147,7 +134,7 @@ module pagetablewalker
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assign MemStore = MemRWM[0];
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// Prefer data address translations over instruction address translations
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assign TranslationVAdr = (SelDataTranslation) ? MemAdrM : PCF; // *** need to register TranslationVAdr
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assign TranslationVAdr = (SelDataTranslation) ? MemAdrM : PCF;
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assign SelDataTranslation = DTLBMissMQ | DTLBMissM;
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flopenrc #(1)
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@ -167,16 +154,10 @@ module pagetablewalker
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.q(ITLBMissFQ));
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assign StartWalk = WalkerState == IDLE && (DTLBMissM | ITLBMissF);
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assign EndWalk = WalkerState == LEAF ||
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//(WalkerState == LEVEL0 && ValidPTE && LeafPTE && ~AccessAlert) ||
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//(WalkerState == LEVEL1 && ValidPTE && LeafPTE && ~AccessAlert) ||
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//(WalkerState == LEVEL2 && ValidPTE && LeafPTE && ~AccessAlert) ||
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//(WalkerState == LEVEL3 && ValidPTE && LeafPTE && ~AccessAlert) ||
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(WalkerState == FAULT);
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assign AnyTLBMissM = DTLBMissM | ITLBMissF;
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assign HPTWTranslate = (DTLBMissMQ | ITLBMissFQ);
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//assign HPTWTranslate = DTLBMissM | ITLBMissF;
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assign StartWalk = WalkerState == IDLE & AnyTLBMissM;
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assign EndWalk = WalkerState == LEAF || WalkerState == FAULT;
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// unswizzle PTE bits
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assign {Dirty, Accessed, Global, User,
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@ -189,9 +170,9 @@ module pagetablewalker
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// Assign specific outputs to general outputs
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assign PageTableEntryF = PageTableEntry;
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//assign PageTableEntryM = PageTableEntry;
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assign PageTableEntryM = PageTableEntry;
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assign PageTypeF = PageType;
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//assign PageTypeM = PageType;
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assign PageTypeM = PageType;
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// generate
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@ -211,26 +192,28 @@ module pagetablewalker
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HPTWReadE = 1'b0;
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PageTableEntry = '0;
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PageType = '0;
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DTLBWriteM_d = '0;
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DTLBWriteM = '0;
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ITLBWriteF = '0;
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WalkerInstrPageFaultF = 1'b0;
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WalkerLoadPageFaultM = 1'b0;
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WalkerStorePageFaultM = 1'b0;
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SelPTW = 1'b1;
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case (WalkerState)
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IDLE: begin
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if (HPTWTranslate && SvMode == `SV32) begin // *** Added SvMode
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NextWalkerState = START;
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SelPTW = 1'b0;
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if (AnyTLBMissM & SvMode == `SV32) begin
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NextWalkerState = LEVEL1_SET_ADRE;
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end else begin
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NextWalkerState = IDLE;
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end
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end
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START: begin
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LEVEL1_SET_ADRE: begin
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NextWalkerState = LEVEL1_WDV;
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TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00};
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HPTWReadE = 1'b1;
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end
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LEVEL1_WDV: begin
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@ -251,15 +234,11 @@ module pagetablewalker
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// supposed to perform that check. However, it is untested.
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if (ValidPTE && LeafPTE && ~BadMegapage) begin
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NextWalkerState = LEAF;
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PageTableEntry = CurrentPTE;
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PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux?
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DTLBWriteM_d = DTLBMissMQ;
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ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
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TranslationPAdr = {2'b00, TranslationVAdr[31:0]};
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end
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// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
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else if (ValidPTE && ~LeafPTE) begin
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NextWalkerState = LEVEL0_WDV;
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NextWalkerState = LEVEL0_SET_ADRE;
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TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
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HPTWReadE = 1'b1;
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end else begin
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@ -267,6 +246,11 @@ module pagetablewalker
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end
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end
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LEVEL0_SET_ADRE: begin
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NextWalkerState = LEVEL0_WDV;
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TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
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end
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LEVEL0_WDV: begin
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TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
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HPTWReadE = 1'b1;
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@ -281,10 +265,6 @@ module pagetablewalker
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LEVEL0: begin
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if (ValidPTE & LeafPTE & ~AccessAlert) begin
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NextWalkerState = LEAF;
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PageTableEntry = CurrentPTE;
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PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00;
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DTLBWriteM_d = DTLBMissMQ;
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ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
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TranslationPAdr = {2'b00, TranslationVAdr[31:0]};
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end else begin
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NextWalkerState = FAULT;
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@ -293,6 +273,11 @@ module pagetablewalker
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LEAF: begin
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NextWalkerState = IDLE;
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PageTableEntry = CurrentPTE;
|
||||
PageType = (PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux?
|
||||
DTLBWriteM = DTLBMissMQ;
|
||||
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
|
||||
TranslationPAdr = {2'b00, TranslationVAdr[31:0]};
|
||||
end
|
||||
|
||||
FAULT: begin
|
||||
@ -356,35 +341,30 @@ module pagetablewalker
|
||||
HPTWReadE = 1'b0;
|
||||
PageTableEntry = '0;
|
||||
PageType = '0;
|
||||
DTLBWriteM_d = '0;
|
||||
DTLBWriteM = '0;
|
||||
ITLBWriteF = '0;
|
||||
|
||||
WalkerInstrPageFaultF = 1'b0;
|
||||
WalkerLoadPageFaultM = 1'b0;
|
||||
WalkerStorePageFaultM = 1'b0;
|
||||
|
||||
SelPTW = 1'b1;
|
||||
|
||||
case (WalkerState)
|
||||
IDLE: begin
|
||||
if (HPTWTranslate && (SvMode == `SV48 || SvMode == `SV39)) begin
|
||||
NextWalkerState = START;
|
||||
SelPTW = 1'b0;
|
||||
if (AnyTLBMissM & SvMode == `SV48) begin
|
||||
NextWalkerState = LEVEL3_SET_ADRE;
|
||||
end else if (AnyTLBMissM & SvMode == `SV39) begin
|
||||
NextWalkerState = LEVEL2_SET_ADRE;
|
||||
end else begin
|
||||
NextWalkerState = IDLE;
|
||||
end
|
||||
end
|
||||
|
||||
START: begin
|
||||
if (HPTWTranslate && SvMode == `SV48) begin
|
||||
LEVEL3_SET_ADRE: begin
|
||||
NextWalkerState = LEVEL3_WDV;
|
||||
TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000};
|
||||
HPTWReadE = 1'b1;
|
||||
end else if (HPTWTranslate && SvMode == `SV39) begin
|
||||
NextWalkerState = LEVEL2_WDV;
|
||||
TranslationPAdr = {BasePageTablePPN, VPN2, 3'b000};
|
||||
HPTWReadE = 1'b1;
|
||||
end else begin // *** should not get here
|
||||
NextWalkerState = IDLE;
|
||||
TranslationPAdr = '0;
|
||||
end
|
||||
end
|
||||
|
||||
LEVEL3_WDV: begin
|
||||
@ -405,23 +385,20 @@ module pagetablewalker
|
||||
// supposed to perform that check. However, it is untested.
|
||||
if (ValidPTE && LeafPTE && ~BadTerapage) begin
|
||||
NextWalkerState = LEAF;
|
||||
PageTableEntry = CurrentPTE;
|
||||
PageType = (WalkerState == LEVEL3) ? 2'b11 : // *** not sure about this mux?
|
||||
((WalkerState == LEVEL2) ? 2'b10 :
|
||||
((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
|
||||
DTLBWriteM_d = DTLBMissMQ;
|
||||
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
|
||||
TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
|
||||
end
|
||||
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
|
||||
else if (ValidPTE && ~LeafPTE) begin
|
||||
NextWalkerState = LEVEL2_WDV;
|
||||
NextWalkerState = LEVEL2_SET_ADRE;
|
||||
TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
|
||||
HPTWReadE = 1'b1;
|
||||
end else begin
|
||||
NextWalkerState = FAULT;
|
||||
end
|
||||
end
|
||||
|
||||
LEVEL2_SET_ADRE: begin
|
||||
NextWalkerState = LEVEL2_WDV;
|
||||
TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
|
||||
end
|
||||
|
||||
LEVEL2_WDV: begin
|
||||
@ -442,23 +419,20 @@ module pagetablewalker
|
||||
// supposed to perform that check. However, it is untested.
|
||||
if (ValidPTE && LeafPTE && ~BadGigapage) begin
|
||||
NextWalkerState = LEAF;
|
||||
PageTableEntry = CurrentPTE;
|
||||
PageType = (WalkerState == LEVEL3) ? 2'b11 :
|
||||
((WalkerState == LEVEL2) ? 2'b10 :
|
||||
((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
|
||||
DTLBWriteM_d = DTLBMissMQ;
|
||||
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
|
||||
TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
|
||||
end
|
||||
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
|
||||
else if (ValidPTE && ~LeafPTE) begin
|
||||
NextWalkerState = LEVEL1_WDV;
|
||||
NextWalkerState = LEVEL1_SET_ADRE;
|
||||
TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
|
||||
HPTWReadE = 1'b1;
|
||||
end else begin
|
||||
NextWalkerState = FAULT;
|
||||
end
|
||||
end
|
||||
|
||||
LEVEL1_SET_ADRE: begin
|
||||
NextWalkerState = LEVEL1_WDV;
|
||||
TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
|
||||
end
|
||||
|
||||
LEVEL1_WDV: begin
|
||||
@ -479,25 +453,23 @@ module pagetablewalker
|
||||
// supposed to perform that check. However, it is untested.
|
||||
if (ValidPTE && LeafPTE && ~BadMegapage) begin
|
||||
NextWalkerState = LEAF;
|
||||
PageTableEntry = CurrentPTE;
|
||||
PageType = (WalkerState == LEVEL3) ? 2'b11 :
|
||||
((WalkerState == LEVEL2) ? 2'b10 :
|
||||
((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
|
||||
DTLBWriteM_d = DTLBMissMQ;
|
||||
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
|
||||
TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
|
||||
|
||||
end
|
||||
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
|
||||
else if (ValidPTE && ~LeafPTE) begin
|
||||
NextWalkerState = LEVEL0_WDV;
|
||||
NextWalkerState = LEVEL0_SET_ADRE;
|
||||
TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
|
||||
HPTWReadE = 1'b1;
|
||||
end else begin
|
||||
NextWalkerState = FAULT;
|
||||
end
|
||||
end
|
||||
|
||||
LEVEL0_SET_ADRE: begin
|
||||
NextWalkerState = LEVEL0_WDV;
|
||||
TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
|
||||
end
|
||||
|
||||
LEVEL0_WDV: begin
|
||||
TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
|
||||
HPTWReadE = 1'b1;
|
||||
@ -512,12 +484,6 @@ module pagetablewalker
|
||||
LEVEL0: begin
|
||||
if (ValidPTE && LeafPTE && ~AccessAlert) begin
|
||||
NextWalkerState = LEAF;
|
||||
PageTableEntry = CurrentPTE;
|
||||
PageType = (WalkerState == LEVEL3) ? 2'b11 :
|
||||
((WalkerState == LEVEL2) ? 2'b10 :
|
||||
((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
|
||||
DTLBWriteM_d = DTLBMissMQ;
|
||||
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
|
||||
TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
|
||||
end else begin
|
||||
NextWalkerState = FAULT;
|
||||
@ -525,6 +491,13 @@ module pagetablewalker
|
||||
end
|
||||
|
||||
LEAF: begin
|
||||
PageTableEntry = CurrentPTE;
|
||||
PageType = (PreviousWalkerState == LEVEL3) ? 2'b11 : // *** not sure about this mux?
|
||||
((PreviousWalkerState == LEVEL2) ? 2'b10 :
|
||||
((PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00));
|
||||
DTLBWriteM = DTLBMissMQ;
|
||||
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
|
||||
TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
|
||||
NextWalkerState = IDLE;
|
||||
end
|
||||
|
||||
@ -568,7 +541,8 @@ module pagetablewalker
|
||||
assign CurrentPTE = SavedPTE;
|
||||
assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10];
|
||||
|
||||
// Assign outputs to ahblite
|
||||
// *** Major issue. We need the full virtual address here.
|
||||
// When the TLB's are update it use use the orignal address
|
||||
// *** Currently truncate address to 32 bits. This must be changed if
|
||||
// we support larger physical address spaces
|
||||
assign HPTWPAdrE = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]};
|
||||
@ -576,11 +550,11 @@ module pagetablewalker
|
||||
//endgenerate
|
||||
end else begin
|
||||
assign HPTWPAdrE = 0;
|
||||
assign HPTWTranslate = 0;
|
||||
assign HPTWReadE = 0;
|
||||
assign WalkerInstrPageFaultF = 0;
|
||||
assign WalkerLoadPageFaultM = 0;
|
||||
assign WalkerStorePageFaultM = 0;
|
||||
assign SelPTW = 0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user