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Updated the ptw, lsuarb and dcache to hopefully solve the interlock issues.

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Ross Thompson 2021-07-16 11:12:57 -05:00
parent f01be12162
commit 5ca7dc619c
4 changed files with 399 additions and 524 deletions
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65
wally-pipelined/src/cache/dcache.sv vendored
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@ -53,6 +53,7 @@ module dcache
input logic DTLBMissM, input logic DTLBMissM,
input logic CacheableM, input logic CacheableM,
input logic DTLBWriteM, input logic DTLBWriteM,
input logic SelPTW,
// ahb side // ahb side
output logic [`PA_BITS-1:0] AHBPAdr, // to ahb output logic [`PA_BITS-1:0] AHBPAdr, // to ahb
output logic AHBRead, output logic AHBRead,
@ -443,7 +444,13 @@ module dcache
// The page table walker asserts it's control 1 cycle // The page table walker asserts it's control 1 cycle
// after the TLBs miss. // after the TLBs miss.
DCacheStall = 1'b1; DCacheStall = 1'b1;
NextState = STATE_READY;
end
else if(SelPTW) begin
// Now we have activated the ptw.
// Do not assert Stall as we are now directing the stall the ptw.
NextState = STATE_PTW_READY; NextState = STATE_PTW_READY;
CommittedM = 1'b1;
end end
// amo hit // amo hit
else if(|AtomicM & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin else if(|AtomicM & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
@ -592,7 +599,7 @@ module dcache
// now all output connect to PTW instead of CPU. // now all output connect to PTW instead of CPU.
CommittedM = 1'b1; CommittedM = 1'b1;
// return to ready if page table walk completed. // return to ready if page table walk completed.
if (DTLBWriteM) begin if (~SelPTW) begin
NextState = STATE_PTW_ACCESS_AFTER_WALK; NextState = STATE_PTW_ACCESS_AFTER_WALK;
// read hit valid cached // read hit valid cached
@ -650,61 +657,15 @@ module dcache
STATE_PTW_READ_MISS_READ_WORD_DELAY: begin STATE_PTW_READ_MISS_READ_WORD_DELAY: begin
SelAdrM = 1'b1; SelAdrM = 1'b1;
NextState = STATE_PTW_READY; NextState = STATE_PTW_READY;
CommittedM = 1'b1; CommittedM = 1'b1;
end end
STATE_PTW_ACCESS_AFTER_WALK: begin STATE_PTW_ACCESS_AFTER_WALK: begin
SelAdrM = 1'b1; DCacheStall = 1'b1;
// amo hit SelAdrM = 1'b1;
if(|AtomicM & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin CommittedM = 1'b1;
NextState = STATE_AMO_UPDATE; NextState = STATE_READY;
DCacheStall = 1'b1;
if(StallW) NextState = STATE_CPU_BUSY;
else NextState = STATE_AMO_UPDATE;
end
// read hit valid cached
else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
DCacheStall = 1'b0;
if(StallW) NextState = STATE_CPU_BUSY;
else NextState = STATE_READY;
end
// write hit valid cached
else if (MemRWM[0] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
DCacheStall = 1'b0;
SRAMWordWriteEnableM = 1'b1;
SetDirtyM = 1'b1;
if(StallW) NextState = STATE_CPU_BUSY;
else NextState = STATE_READY;
end
// read or write miss valid cached
else if((|MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & ~CacheHit & ~DTLBMissM) begin
NextState = STATE_MISS_FETCH_WDV;
CntReset = 1'b1;
DCacheStall = 1'b1;
end
// uncached write
else if(MemRWM[0] & ~CacheableM & ~ExceptionM & ~DTLBMissM) begin
NextState = STATE_UNCACHED_WRITE;
CntReset = 1'b1;
DCacheStall = 1'b1;
AHBWrite = 1'b1;
end
// uncached read
else if(MemRWM[1] & ~CacheableM & ~ExceptionM & ~DTLBMissM) begin
NextState = STATE_UNCACHED_READ;
CntReset = 1'b1;
DCacheStall = 1'b1;
AHBRead = 1'b1;
end
// fault
else if(AnyCPUReqM & (ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
NextState = STATE_READY;
end
else NextState = STATE_READY;
end end
STATE_CPU_BUSY : begin STATE_CPU_BUSY : begin

13
wally-pipelined/src/lsu/lsu.sv
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@ -126,7 +126,6 @@ module lsu
logic HPTWStall; logic HPTWStall;
logic [`XLEN-1:0] HPTWPAdrE; logic [`XLEN-1:0] HPTWPAdrE;
logic [`XLEN-1:0] HPTWPAdrM; logic [`XLEN-1:0] HPTWPAdrM;
logic HPTWTranslate;
logic HPTWReadM; logic HPTWReadM;
logic [1:0] MemRWMtoDCache; logic [1:0] MemRWMtoDCache;
logic [2:0] Funct3MtoDCache; logic [2:0] Funct3MtoDCache;
@ -170,8 +169,8 @@ module lsu
.HPTWStall(HPTWStall), .HPTWStall(HPTWStall),
.HPTWPAdrE(HPTWPAdrE), .HPTWPAdrE(HPTWPAdrE),
.HPTWPAdrM(HPTWPAdrM), .HPTWPAdrM(HPTWPAdrM),
.HPTWTranslate(HPTWTranslate),
.HPTWReadM(HPTWReadM), .HPTWReadM(HPTWReadM),
.SelPTW(SelPTW),
.WalkerInstrPageFaultF(WalkerInstrPageFaultF), .WalkerInstrPageFaultF(WalkerInstrPageFaultF),
.WalkerLoadPageFaultM(WalkerLoadPageFaultM), .WalkerLoadPageFaultM(WalkerLoadPageFaultM),
.WalkerStorePageFaultM(WalkerStorePageFaultM)); .WalkerStorePageFaultM(WalkerStorePageFaultM));
@ -182,7 +181,7 @@ module lsu
lsuArb arbiter(.clk(clk), lsuArb arbiter(.clk(clk),
.reset(reset), .reset(reset),
// HPTW connection // HPTW connection
.HPTWTranslate(HPTWTranslate), .SelPTW(SelPTW),
.HPTWReadM(HPTWReadM), .HPTWReadM(HPTWReadM),
.HPTWPAdrE(HPTWPAdrE), .HPTWPAdrE(HPTWPAdrE),
.HPTWPAdrM(HPTWPAdrM), .HPTWPAdrM(HPTWPAdrM),
@ -214,8 +213,9 @@ module lsu
.ReadDataWfromDCache(ReadDataWfromDCache), .ReadDataWfromDCache(ReadDataWfromDCache),
.CommittedMfromDCache(CommittedMfromDCache), .CommittedMfromDCache(CommittedMfromDCache),
.PendingInterruptMtoDCache(PendingInterruptMtoDCache), .PendingInterruptMtoDCache(PendingInterruptMtoDCache),
.DCacheStall(DCacheStall), .DCacheStall(DCacheStall));
.SelPTW(SelPTW));
mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
@ -243,7 +243,9 @@ module lsu
// .SelRegions(DHSELRegionsM), // .SelRegions(DHSELRegionsM),
.*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist? .*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist?
// *** BUG, this is most likely wrong
assign CacheableMtoDCache = SelPTW ? 1'b1 : CacheableM; assign CacheableMtoDCache = SelPTW ? 1'b1 : CacheableM;
generate generate
if (`XLEN == 32) assign DCtoAHBSizeM = CacheableMtoDCache ? 3'b010 : Funct3MtoDCache; if (`XLEN == 32) assign DCtoAHBSizeM = CacheableMtoDCache ? 3'b010 : Funct3MtoDCache;
else assign DCtoAHBSizeM = CacheableMtoDCache ? 3'b011 : Funct3MtoDCache; else assign DCtoAHBSizeM = CacheableMtoDCache ? 3'b011 : Funct3MtoDCache;
@ -335,6 +337,7 @@ module lsu
.DTLBMissM(DTLBMissM), .DTLBMissM(DTLBMissM),
.CacheableM(CacheableMtoDCache), .CacheableM(CacheableMtoDCache),
.DTLBWriteM(DTLBWriteM), .DTLBWriteM(DTLBWriteM),
.SelPTW(SelPTW),
// AHB connection // AHB connection
.AHBPAdr(DCtoAHBPAdrM), .AHBPAdr(DCtoAHBPAdrM),

65
wally-pipelined/src/lsu/lsuArb.sv
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@ -30,7 +30,7 @@ module lsuArb
(input logic clk, reset, (input logic clk, reset,
// from page table walker // from page table walker
input logic HPTWTranslate, input logic SelPTW,
input logic HPTWReadM, input logic HPTWReadM,
input logic [`XLEN-1:0] HPTWPAdrE, input logic [`XLEN-1:0] HPTWPAdrE,
input logic [`XLEN-1:0] HPTWPAdrM, input logic [`XLEN-1:0] HPTWPAdrM,
@ -62,7 +62,6 @@ module lsuArb
output logic [`XLEN-1:0] MemAdrEtoDCache, output logic [`XLEN-1:0] MemAdrEtoDCache,
output logic StallWtoDCache, output logic StallWtoDCache,
output logic PendingInterruptMtoDCache, output logic PendingInterruptMtoDCache,
output logic SelPTW,
// from D Cache // from D Cache
@ -74,72 +73,10 @@ module lsuArb
); );
// HPTWTranslate is the request for memory by the page table walker. When
// this is high the page table walker gains priority over the CPU's data
// input. Note the ptw only makes a request after an instruction or data
// tlb miss. It is entirely possible the dcache is currently processing
// a data cache miss when an instruction tlb miss occurs. If an instruction
// in the E stage causes a d cache miss, the d cache will immediately start
// processing the request. Simultaneously the ITLB misses. By the time
// the TLB miss causes the page table walker to issue the first request
// to data memory the d cache is already busy. We can interlock by
// leveraging Stall as a d cache busy. We will need an FSM to handle this.
typedef enum{StateReady,
StatePTWPending,
StatePTWActive} statetype;
statetype CurrState, NextState;
logic [2:0] PTWSize; logic [2:0] PTWSize;
flopenl #(.TYPE(statetype)) StateReg(.clk(clk),
.load(reset),
.en(1'b1),
.d(NextState),
.val(StateReady),
.q(CurrState));
always_comb begin
case(CurrState)
StateReady:
if (HPTWTranslate) NextState = StatePTWActive;
else NextState = StateReady;
StatePTWActive:
if (HPTWTranslate) NextState = StatePTWActive;
else NextState = StateReady;
default: NextState = StateReady;
endcase
end
/* -----\/----- EXCLUDED -----\/-----
always_comb begin
case(CurrState)
StateReady:
/-* -----\/----- EXCLUDED -----\/-----
if (HPTWTranslate & DataStall) NextState = StatePTWPending;
else
-----/\----- EXCLUDED -----/\----- *-/
if (HPTWTranslate) NextState = StatePTWActive;
else NextState = StateReady;
StatePTWPending:
if (HPTWTranslate & ~DataStall) NextState = StatePTWActive;
else if (HPTWTranslate & DataStall) NextState = StatePTWPending;
else NextState = StateReady;
StatePTWActive:
if (HPTWTranslate) NextState = StatePTWActive;
else NextState = StateReady;
default: NextState = StateReady;
endcase
end
-----/\----- EXCLUDED -----/\----- */
// multiplex the outputs to LSU // multiplex the outputs to LSU
assign DisableTranslation = SelPTW; // change names between SelPTW would be confusing in DTLB. assign DisableTranslation = SelPTW; // change names between SelPTW would be confusing in DTLB.
assign SelPTW = (CurrState == StatePTWActive && HPTWTranslate) || (CurrState == StateReady && HPTWTranslate);
assign MemRWMtoDCache = SelPTW ? {HPTWReadM, 1'b0} : MemRWM; assign MemRWMtoDCache = SelPTW ? {HPTWReadM, 1'b0} : MemRWM;
generate generate

722
wally-pipelined/src/mmu/pagetablewalker.sv
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@ -37,107 +37,94 @@
module pagetablewalker module pagetablewalker
( (
// Control signals // Control signals
input logic clk, reset, input logic clk, reset,
input logic [`XLEN-1:0] SATP_REGW, input logic [`XLEN-1:0] SATP_REGW,
// Signals from TLBs (addresses to translate) // Signals from TLBs (addresses to translate)
input logic [`XLEN-1:0] PCF, MemAdrM, input logic [`XLEN-1:0] PCF, MemAdrM,
input logic ITLBMissF, DTLBMissM, input logic ITLBMissF, DTLBMissM,
input logic [1:0] MemRWM, input logic [1:0] MemRWM,
// Outputs to the TLBs (PTEs to write) // Outputs to the TLBs (PTEs to write)
output logic [`XLEN-1:0] PageTableEntryF, PageTableEntryM, output logic [`XLEN-1:0] PageTableEntryF, PageTableEntryM,
output logic [1:0] PageTypeF, PageTypeM, output logic [1:0] PageTypeF, PageTypeM,
output logic ITLBWriteF, DTLBWriteM, output logic ITLBWriteF, DTLBWriteM,
output logic SelPTW,
// *** modify to send to LSU // *** KMG: These are inputs/results from the ahblite whose addresses should have already been checked, so I don't think they need to be sent through the LSU // *** modify to send to LSU // *** KMG: These are inputs/results from the ahblite whose addresses should have already been checked, so I don't think they need to be sent through the LSU
input logic [`XLEN-1:0] HPTWReadPTE, input logic [`XLEN-1:0] HPTWReadPTE,
input logic MMUReady, input logic MMUReady,
input logic HPTWStall, input logic HPTWStall,
// *** modify to send to LSU // *** modify to send to LSU
output logic [`XLEN-1:0] HPTWPAdrE, // this probalby should be `PA_BITS wide output logic [`XLEN-1:0] HPTWPAdrE, // this probalby should be `PA_BITS wide
output logic [`XLEN-1:0] HPTWPAdrM, // this probalby should be `PA_BITS wide output logic [`XLEN-1:0] HPTWPAdrM, // this probalby should be `PA_BITS wide
output logic HPTWTranslate, // *** rename to HPTWReq output logic HPTWReadM,
output logic HPTWReadM,
// Faults // Faults
output logic WalkerInstrPageFaultF, output logic WalkerInstrPageFaultF,
output logic WalkerLoadPageFaultM, output logic WalkerLoadPageFaultM,
output logic WalkerStorePageFaultM output logic WalkerStorePageFaultM
); );
logic HPTWReadE; logic HPTWReadE;
generate generate
if (`MEM_VIRTMEM) begin if (`MEM_VIRTMEM) begin
// Internal signals // Internal signals
// register TLBs translation miss requests // register TLBs translation miss requests
logic ITLBMissFQ, DTLBMissMQ; logic ITLBMissFQ, DTLBMissMQ;
logic [`PPN_BITS-1:0] BasePageTablePPN; logic [`PPN_BITS-1:0] BasePageTablePPN;
logic [`XLEN-1:0] TranslationVAdr; logic [`XLEN-1:0] TranslationVAdr;
logic [`XLEN-1:0] SavedPTE, CurrentPTE; logic [`XLEN-1:0] SavedPTE, CurrentPTE;
logic [`PA_BITS-1:0] TranslationPAdr; logic [`PA_BITS-1:0] TranslationPAdr;
logic [`PPN_BITS-1:0] CurrentPPN; logic [`PPN_BITS-1:0] CurrentPPN;
logic [`SVMODE_BITS-1:0] SvMode; logic [`SVMODE_BITS-1:0] SvMode;
logic MemStore; logic MemStore;
logic DTLBWriteM_d;
// PTE Control Bits // PTE Control Bits
logic Dirty, Accessed, Global, User, logic Dirty, Accessed, Global, User,
Executable, Writable, Readable, Valid; Executable, Writable, Readable, Valid;
// PTE descriptions // PTE descriptions
logic ValidPTE, AccessAlert, MegapageMisaligned, BadMegapage, LeafPTE; logic ValidPTE, AccessAlert, MegapageMisaligned, BadMegapage, LeafPTE;
// Outputs of walker // Outputs of walker
logic [`XLEN-1:0] PageTableEntry; logic [`XLEN-1:0] PageTableEntry;
logic [1:0] PageType; logic [1:0] PageType;
logic StartWalk; logic StartWalk;
logic EndWalk; logic EndWalk;
typedef enum {LEVEL0_WDV, typedef enum {LEVEL0_SET_ADRE,
LEVEL0_WDV,
LEVEL0, LEVEL0,
LEVEL1_SET_ADRE,
LEVEL1_WDV, LEVEL1_WDV,
LEVEL1, LEVEL1,
LEVEL2_SET_ADRE,
LEVEL2_WDV, LEVEL2_WDV,
LEVEL2, LEVEL2,
LEVEL3_SET_ADRE,
LEVEL3_WDV, LEVEL3_WDV,
LEVEL3, LEVEL3,
LEAF, LEAF,
IDLE, IDLE,
START,
FAULT} statetype; FAULT} statetype;
statetype WalkerState, NextWalkerState; statetype WalkerState, NextWalkerState, PreviousWalkerState;
logic PRegEn; logic PRegEn;
logic SelDataTranslation; logic SelDataTranslation;
logic AnyTLBMissM;
flop #(`XLEN) HPTWPAdrMReg(.clk(clk),
.d(HPTWPAdrE),
.q(HPTWPAdrM));
flop #(2) PageTypeReg(.clk(clk), flop #(`XLEN) HPTWPAdrMReg(.clk(clk),
.d(PageType), .d(HPTWPAdrE),
.q(PageTypeM)); .q(HPTWPAdrM));
flop #(`XLEN) PageTableEntryReg(.clk(clk),
.d(PageTableEntry),
.q(PageTableEntryM));
flop #(1) DTLBWriteReg(.clk(clk),
.d(DTLBWriteM_d),
.q(DTLBWriteM));
flop #(1) HPTWReadMReg(.clk(clk),
.d(HPTWReadE),
.q(HPTWReadM));
assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]; assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
@ -147,7 +134,7 @@ module pagetablewalker
assign MemStore = MemRWM[0]; assign MemStore = MemRWM[0];
// Prefer data address translations over instruction address translations // Prefer data address translations over instruction address translations
assign TranslationVAdr = (SelDataTranslation) ? MemAdrM : PCF; // *** need to register TranslationVAdr assign TranslationVAdr = (SelDataTranslation) ? MemAdrM : PCF;
assign SelDataTranslation = DTLBMissMQ | DTLBMissM; assign SelDataTranslation = DTLBMissMQ | DTLBMissM;
flopenrc #(1) flopenrc #(1)
@ -167,20 +154,14 @@ module pagetablewalker
.q(ITLBMissFQ)); .q(ITLBMissFQ));
assign StartWalk = WalkerState == IDLE && (DTLBMissM | ITLBMissF); assign AnyTLBMissM = DTLBMissM | ITLBMissF;
assign EndWalk = WalkerState == LEAF ||
//(WalkerState == LEVEL0 && ValidPTE && LeafPTE && ~AccessAlert) ||
//(WalkerState == LEVEL1 && ValidPTE && LeafPTE && ~AccessAlert) ||
//(WalkerState == LEVEL2 && ValidPTE && LeafPTE && ~AccessAlert) ||
//(WalkerState == LEVEL3 && ValidPTE && LeafPTE && ~AccessAlert) ||
(WalkerState == FAULT);
assign HPTWTranslate = (DTLBMissMQ | ITLBMissFQ); assign StartWalk = WalkerState == IDLE & AnyTLBMissM;
//assign HPTWTranslate = DTLBMissM | ITLBMissF; assign EndWalk = WalkerState == LEAF || WalkerState == FAULT;
// unswizzle PTE bits // unswizzle PTE bits
assign {Dirty, Accessed, Global, User, assign {Dirty, Accessed, Global, User,
Executable, Writable, Readable, Valid} = CurrentPTE[7:0]; Executable, Writable, Readable, Valid} = CurrentPTE[7:0];
// Assign PTE descriptors common across all XLEN values // Assign PTE descriptors common across all XLEN values
assign LeafPTE = Executable | Writable | Readable; assign LeafPTE = Executable | Writable | Readable;
@ -189,398 +170,391 @@ module pagetablewalker
// Assign specific outputs to general outputs // Assign specific outputs to general outputs
assign PageTableEntryF = PageTableEntry; assign PageTableEntryF = PageTableEntry;
//assign PageTableEntryM = PageTableEntry; assign PageTableEntryM = PageTableEntry;
assign PageTypeF = PageType; assign PageTypeF = PageType;
//assign PageTypeM = PageType; assign PageTypeM = PageType;
// generate // generate
if (`XLEN == 32) begin if (`XLEN == 32) begin
logic [9:0] VPN1, VPN0; logic [9:0] VPN1, VPN0;
flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
/* -----\/----- EXCLUDED -----\/----- /* -----\/----- EXCLUDED -----\/-----
assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV) && ~HPTWStall; assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV) && ~HPTWStall;
-----/\----- EXCLUDED -----/\----- */ -----/\----- EXCLUDED -----/\----- */
// State transition logic // State transition logic
always_comb begin always_comb begin
PRegEn = 1'b0; PRegEn = 1'b0;
TranslationPAdr = '0; TranslationPAdr = '0;
HPTWReadE = 1'b0; HPTWReadE = 1'b0;
PageTableEntry = '0; PageTableEntry = '0;
PageType = '0; PageType = '0;
DTLBWriteM_d = '0; DTLBWriteM = '0;
ITLBWriteF = '0; ITLBWriteF = '0;
WalkerInstrPageFaultF = 1'b0; WalkerInstrPageFaultF = 1'b0;
WalkerLoadPageFaultM = 1'b0; WalkerLoadPageFaultM = 1'b0;
WalkerStorePageFaultM = 1'b0; WalkerStorePageFaultM = 1'b0;
case (WalkerState) SelPTW = 1'b1;
IDLE: begin
if (HPTWTranslate && SvMode == `SV32) begin // *** Added SvMode
NextWalkerState = START;
end else begin
NextWalkerState = IDLE;
end
end
START: begin case (WalkerState)
NextWalkerState = LEVEL1_WDV; IDLE: begin
TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; SelPTW = 1'b0;
HPTWReadE = 1'b1; if (AnyTLBMissM & SvMode == `SV32) begin
end NextWalkerState = LEVEL1_SET_ADRE;
end else begin
NextWalkerState = IDLE;
end
end
LEVEL1_WDV: begin LEVEL1_SET_ADRE: begin
TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; NextWalkerState = LEVEL1_WDV;
HPTWReadE = 1'b1; TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00};
if (HPTWStall) begin end
NextWalkerState = LEVEL1_WDV;
end else begin LEVEL1_WDV: begin
NextWalkerState = LEVEL1; TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00};
HPTWReadE = 1'b1;
if (HPTWStall) begin
NextWalkerState = LEVEL1_WDV;
end else begin
NextWalkerState = LEVEL1;
PRegEn = 1'b1; PRegEn = 1'b1;
end end
end end
LEVEL1: begin LEVEL1: begin
// *** <FUTURE WORK> According to the architecture, we should // *** <FUTURE WORK> According to the architecture, we should
// fault upon finding a superpage that is misaligned or has 0 // fault upon finding a superpage that is misaligned or has 0
// access bit. The following commented line of code is // access bit. The following commented line of code is
// supposed to perform that check. However, it is untested. // supposed to perform that check. However, it is untested.
if (ValidPTE && LeafPTE && ~BadMegapage) begin if (ValidPTE && LeafPTE && ~BadMegapage) begin
NextWalkerState = LEAF; NextWalkerState = LEAF;
PageTableEntry = CurrentPTE; TranslationPAdr = {2'b00, TranslationVAdr[31:0]};
PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux? end
DTLBWriteM_d = DTLBMissMQ; // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions else if (ValidPTE && ~LeafPTE) begin
TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; NextWalkerState = LEVEL0_SET_ADRE;
end TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
else if (ValidPTE && ~LeafPTE) begin
NextWalkerState = LEVEL0_WDV;
TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
HPTWReadE = 1'b1; HPTWReadE = 1'b1;
end else begin end else begin
NextWalkerState = FAULT; NextWalkerState = FAULT;
end end
end end
LEVEL0_WDV: begin LEVEL0_SET_ADRE: begin
TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; NextWalkerState = LEVEL0_WDV;
HPTWReadE = 1'b1; TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
if (HPTWStall) begin end
LEVEL0_WDV: begin
TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
HPTWReadE = 1'b1;
if (HPTWStall) begin
NextWalkerState = LEVEL0_WDV; NextWalkerState = LEVEL0_WDV;
end else begin end else begin
NextWalkerState = LEVEL0; NextWalkerState = LEVEL0;
PRegEn = 1'b1; PRegEn = 1'b1;
end end
end end
LEVEL0: begin LEVEL0: begin
if (ValidPTE & LeafPTE & ~AccessAlert) begin if (ValidPTE & LeafPTE & ~AccessAlert) begin
NextWalkerState = LEAF; NextWalkerState = LEAF;
PageTableEntry = CurrentPTE; TranslationPAdr = {2'b00, TranslationVAdr[31:0]};
PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00; end else begin
DTLBWriteM_d = DTLBMissMQ; NextWalkerState = FAULT;
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions end
TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; end
end else begin
NextWalkerState = FAULT;
end
end
LEAF: begin LEAF: begin
NextWalkerState = IDLE; NextWalkerState = IDLE;
end PageTableEntry = CurrentPTE;
PageType = (PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux?
DTLBWriteM = DTLBMissMQ;
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
TranslationPAdr = {2'b00, TranslationVAdr[31:0]};
end
FAULT: begin FAULT: begin
NextWalkerState = IDLE; NextWalkerState = IDLE;
WalkerInstrPageFaultF = ~DTLBMissMQ; WalkerInstrPageFaultF = ~DTLBMissMQ;
WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore;
WalkerStorePageFaultM = DTLBMissMQ && MemStore; WalkerStorePageFaultM = DTLBMissMQ && MemStore;
end end
// Default case should never happen, but is included for linter. // Default case should never happen, but is included for linter.
default: NextWalkerState = IDLE; default: NextWalkerState = IDLE;
endcase endcase
end end
// A megapage is a Level 1 leaf page. This page must have zero PPN[0]. // A megapage is a Level 1 leaf page. This page must have zero PPN[0].
assign MegapageMisaligned = |(CurrentPPN[9:0]); assign MegapageMisaligned = |(CurrentPPN[9:0]);
assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
assign VPN1 = TranslationVAdr[31:22]; assign VPN1 = TranslationVAdr[31:22];
assign VPN0 = TranslationVAdr[21:12]; assign VPN0 = TranslationVAdr[21:12];
// Capture page table entry from data cache // Capture page table entry from data cache
// *** may need to delay reading this value until the next clock cycle. // *** may need to delay reading this value until the next clock cycle.
// The clk to q latency of the SRAM in the data cache will be long. // The clk to q latency of the SRAM in the data cache will be long.
// I cannot see directly using this value. This is no different than // I cannot see directly using this value. This is no different than
// a load delay hazard. This will require rewriting the walker fsm. // a load delay hazard. This will require rewriting the walker fsm.
// also need a new signal to save. Should be a mealy output of the fsm // also need a new signal to save. Should be a mealy output of the fsm
// request followed by ~stall. // request followed by ~stall.
flopenr #(32) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE); flopenr #(32) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE);
//mux2 #(32) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE); //mux2 #(32) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE);
assign CurrentPTE = SavedPTE; assign CurrentPTE = SavedPTE;
assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10]; assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10];
// Assign outputs to ahblite // Assign outputs to ahblite
// *** Currently truncate address to 32 bits. This must be changed if // *** Currently truncate address to 32 bits. This must be changed if
// we support larger physical address spaces // we support larger physical address spaces
assign HPTWPAdrE = TranslationPAdr[31:0]; assign HPTWPAdrE = TranslationPAdr[31:0];
end else begin end else begin
logic [8:0] VPN3, VPN2, VPN1, VPN0; logic [8:0] VPN3, VPN2, VPN1, VPN0;
logic TerapageMisaligned, GigapageMisaligned, BadTerapage, BadGigapage; logic TerapageMisaligned, GigapageMisaligned, BadTerapage, BadGigapage;
flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
/* -----\/----- EXCLUDED -----\/----- /* -----\/----- EXCLUDED -----\/-----
assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV || assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV ||
WalkerState == LEVEL2_WDV || WalkerState == LEVEL3_WDV) && ~HPTWStall; WalkerState == LEVEL2_WDV || WalkerState == LEVEL3_WDV) && ~HPTWStall;
-----/\----- EXCLUDED -----/\----- */ -----/\----- EXCLUDED -----/\----- */
//assign HPTWRead = (WalkerState == IDLE && HPTWTranslate) || WalkerState == LEVEL3 || //assign HPTWRead = (WalkerState == IDLE && HPTWTranslate) || WalkerState == LEVEL3 ||
// WalkerState == LEVEL2 || WalkerState == LEVEL1; // WalkerState == LEVEL2 || WalkerState == LEVEL1;
always_comb begin always_comb begin
PRegEn = 1'b0; PRegEn = 1'b0;
TranslationPAdr = '0; TranslationPAdr = '0;
HPTWReadE = 1'b0; HPTWReadE = 1'b0;
PageTableEntry = '0; PageTableEntry = '0;
PageType = '0; PageType = '0;
DTLBWriteM_d = '0; DTLBWriteM = '0;
ITLBWriteF = '0; ITLBWriteF = '0;
WalkerInstrPageFaultF = 1'b0; WalkerInstrPageFaultF = 1'b0;
WalkerLoadPageFaultM = 1'b0; WalkerLoadPageFaultM = 1'b0;
WalkerStorePageFaultM = 1'b0; WalkerStorePageFaultM = 1'b0;
case (WalkerState) SelPTW = 1'b1;
IDLE: begin
if (HPTWTranslate && (SvMode == `SV48 || SvMode == `SV39)) begin
NextWalkerState = START;
end else begin
NextWalkerState = IDLE;
end
end
START: begin case (WalkerState)
if (HPTWTranslate && SvMode == `SV48) begin IDLE: begin
SelPTW = 1'b0;
if (AnyTLBMissM & SvMode == `SV48) begin
NextWalkerState = LEVEL3_SET_ADRE;
end else if (AnyTLBMissM & SvMode == `SV39) begin
NextWalkerState = LEVEL2_SET_ADRE;
end else begin
NextWalkerState = IDLE;
end
end
LEVEL3_SET_ADRE: begin
NextWalkerState = LEVEL3_WDV;
TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000};
end
LEVEL3_WDV: begin
TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000};
HPTWReadE = 1'b1;
if (HPTWStall) begin
NextWalkerState = LEVEL3_WDV; NextWalkerState = LEVEL3_WDV;
TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000}; end else begin
HPTWReadE = 1'b1;
end else if (HPTWTranslate && SvMode == `SV39) begin
NextWalkerState = LEVEL2_WDV;
TranslationPAdr = {BasePageTablePPN, VPN2, 3'b000};
HPTWReadE = 1'b1;
end else begin // *** should not get here
NextWalkerState = IDLE;
TranslationPAdr = '0;
end
end
LEVEL3_WDV: begin
TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000};
HPTWReadE = 1'b1;
if (HPTWStall) begin
NextWalkerState = LEVEL3_WDV;
end else begin
NextWalkerState = LEVEL3; NextWalkerState = LEVEL3;
PRegEn = 1'b1; PRegEn = 1'b1;
end end
end end
LEVEL3: begin LEVEL3: begin
// *** <FUTURE WORK> According to the architecture, we should // *** <FUTURE WORK> According to the architecture, we should
// fault upon finding a superpage that is misaligned or has 0 // fault upon finding a superpage that is misaligned or has 0
// access bit. The following commented line of code is // access bit. The following commented line of code is
// supposed to perform that check. However, it is untested. // supposed to perform that check. However, it is untested.
if (ValidPTE && LeafPTE && ~BadTerapage) begin if (ValidPTE && LeafPTE && ~BadTerapage) begin
NextWalkerState = LEAF; NextWalkerState = LEAF;
PageTableEntry = CurrentPTE; TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
PageType = (WalkerState == LEVEL3) ? 2'b11 : // *** not sure about this mux? end
((WalkerState == LEVEL2) ? 2'b10 : // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); else if (ValidPTE && ~LeafPTE) begin
DTLBWriteM_d = DTLBMissMQ; NextWalkerState = LEVEL2_SET_ADRE;
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; end else begin
end NextWalkerState = FAULT;
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. end
else if (ValidPTE && ~LeafPTE) begin end
NextWalkerState = LEVEL2_WDV;
TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
HPTWReadE = 1'b1;
end else begin
NextWalkerState = FAULT;
end
end LEVEL2_SET_ADRE: begin
NextWalkerState = LEVEL2_WDV;
TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
end
LEVEL2_WDV: begin LEVEL2_WDV: begin
TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000}; TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
HPTWReadE = 1'b1; HPTWReadE = 1'b1;
if (HPTWStall) begin if (HPTWStall) begin
NextWalkerState = LEVEL2_WDV; NextWalkerState = LEVEL2_WDV;
end else begin end else begin
NextWalkerState = LEVEL2; NextWalkerState = LEVEL2;
PRegEn = 1'b1; PRegEn = 1'b1;
end end
end end
LEVEL2: begin LEVEL2: begin
// *** <FUTURE WORK> According to the architecture, we should // *** <FUTURE WORK> According to the architecture, we should
// fault upon finding a superpage that is misaligned or has 0 // fault upon finding a superpage that is misaligned or has 0
// access bit. The following commented line of code is // access bit. The following commented line of code is
// supposed to perform that check. However, it is untested. // supposed to perform that check. However, it is untested.
if (ValidPTE && LeafPTE && ~BadGigapage) begin if (ValidPTE && LeafPTE && ~BadGigapage) begin
NextWalkerState = LEAF; NextWalkerState = LEAF;
PageTableEntry = CurrentPTE; TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
PageType = (WalkerState == LEVEL3) ? 2'b11 : end
((WalkerState == LEVEL2) ? 2'b10 : // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); else if (ValidPTE && ~LeafPTE) begin
DTLBWriteM_d = DTLBMissMQ; NextWalkerState = LEVEL1_SET_ADRE;
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; end else begin
end NextWalkerState = FAULT;
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. end
else if (ValidPTE && ~LeafPTE) begin end
NextWalkerState = LEVEL1_WDV;
TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
HPTWReadE = 1'b1;
end else begin
NextWalkerState = FAULT;
end
end LEVEL1_SET_ADRE: begin
NextWalkerState = LEVEL1_WDV;
TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
end
LEVEL1_WDV: begin LEVEL1_WDV: begin
TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
HPTWReadE = 1'b1; HPTWReadE = 1'b1;
if (HPTWStall) begin if (HPTWStall) begin
NextWalkerState = LEVEL1_WDV; NextWalkerState = LEVEL1_WDV;
end else begin end else begin
NextWalkerState = LEVEL1; NextWalkerState = LEVEL1;
PRegEn = 1'b1; PRegEn = 1'b1;
end end
end end
LEVEL1: begin LEVEL1: begin
// *** <FUTURE WORK> According to the architecture, we should // *** <FUTURE WORK> According to the architecture, we should
// fault upon finding a superpage that is misaligned or has 0 // fault upon finding a superpage that is misaligned or has 0
// access bit. The following commented line of code is // access bit. The following commented line of code is
// supposed to perform that check. However, it is untested. // supposed to perform that check. However, it is untested.
if (ValidPTE && LeafPTE && ~BadMegapage) begin if (ValidPTE && LeafPTE && ~BadMegapage) begin
NextWalkerState = LEAF; NextWalkerState = LEAF;
PageTableEntry = CurrentPTE; TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
PageType = (WalkerState == LEVEL3) ? 2'b11 :
((WalkerState == LEVEL2) ? 2'b10 :
((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
DTLBWriteM_d = DTLBMissMQ;
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
end end
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
else if (ValidPTE && ~LeafPTE) begin else if (ValidPTE && ~LeafPTE) begin
NextWalkerState = LEVEL0_WDV; NextWalkerState = LEVEL0_SET_ADRE;
TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
HPTWReadE = 1'b1; end else begin
end else begin NextWalkerState = FAULT;
NextWalkerState = FAULT; end
end end
end
LEVEL0_WDV: begin LEVEL0_SET_ADRE: begin
TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; NextWalkerState = LEVEL0_WDV;
HPTWReadE = 1'b1; TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
if (HPTWStall) begin end
NextWalkerState = LEVEL0_WDV;
end else begin
NextWalkerState = LEVEL0;
PRegEn = 1'b1;
end
end
LEVEL0: begin LEVEL0_WDV: begin
if (ValidPTE && LeafPTE && ~AccessAlert) begin TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
NextWalkerState = LEAF; HPTWReadE = 1'b1;
PageTableEntry = CurrentPTE; if (HPTWStall) begin
PageType = (WalkerState == LEVEL3) ? 2'b11 : NextWalkerState = LEVEL0_WDV;
((WalkerState == LEVEL2) ? 2'b10 : end else begin
((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); NextWalkerState = LEVEL0;
DTLBWriteM_d = DTLBMissMQ; PRegEn = 1'b1;
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions end
TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; end
end else begin
NextWalkerState = FAULT;
end
end
LEAF: begin LEVEL0: begin
NextWalkerState = IDLE; if (ValidPTE && LeafPTE && ~AccessAlert) begin
end NextWalkerState = LEAF;
TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
end else begin
NextWalkerState = FAULT;
end
end
FAULT: begin LEAF: begin
NextWalkerState = IDLE; PageTableEntry = CurrentPTE;
WalkerInstrPageFaultF = ~DTLBMissMQ; PageType = (PreviousWalkerState == LEVEL3) ? 2'b11 : // *** not sure about this mux?
WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; ((PreviousWalkerState == LEVEL2) ? 2'b10 :
WalkerStorePageFaultM = DTLBMissMQ && MemStore; ((PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00));
end DTLBWriteM = DTLBMissMQ;
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
NextWalkerState = IDLE;
end
// Default case should never happen FAULT: begin
default: begin NextWalkerState = IDLE;
NextWalkerState = IDLE; WalkerInstrPageFaultF = ~DTLBMissMQ;
end WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore;
WalkerStorePageFaultM = DTLBMissMQ && MemStore;
end
endcase // Default case should never happen
end default: begin
NextWalkerState = IDLE;
end
// A terapage is a level 3 leaf page. This page must have zero PPN[2], endcase
// zero PPN[1], and zero PPN[0] end
assign TerapageMisaligned = |(CurrentPPN[26:0]);
// A gigapage is a Level 2 leaf page. This page must have zero PPN[1] and
// zero PPN[0]
assign GigapageMisaligned = |(CurrentPPN[17:0]);
// A megapage is a Level 1 leaf page. This page must have zero PPN[0].
assign MegapageMisaligned = |(CurrentPPN[8:0]);
assign BadTerapage = TerapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme // A terapage is a level 3 leaf page. This page must have zero PPN[2],
assign BadGigapage = GigapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme // zero PPN[1], and zero PPN[0]
assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme assign TerapageMisaligned = |(CurrentPPN[26:0]);
// A gigapage is a Level 2 leaf page. This page must have zero PPN[1] and
// zero PPN[0]
assign GigapageMisaligned = |(CurrentPPN[17:0]);
// A megapage is a Level 1 leaf page. This page must have zero PPN[0].
assign MegapageMisaligned = |(CurrentPPN[8:0]);
assign VPN3 = TranslationVAdr[47:39]; assign BadTerapage = TerapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
assign VPN2 = TranslationVAdr[38:30]; assign BadGigapage = GigapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
assign VPN1 = TranslationVAdr[29:21]; assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
assign VPN0 = TranslationVAdr[20:12];
assign VPN3 = TranslationVAdr[47:39];
assign VPN2 = TranslationVAdr[38:30];
assign VPN1 = TranslationVAdr[29:21];
assign VPN0 = TranslationVAdr[20:12];
// Capture page table entry from ahblite // Capture page table entry from ahblite
flopenr #(`XLEN) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE); flopenr #(`XLEN) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE);
//mux2 #(`XLEN) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE); //mux2 #(`XLEN) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE);
assign CurrentPTE = SavedPTE; assign CurrentPTE = SavedPTE;
assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10]; assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10];
// Assign outputs to ahblite // *** Major issue. We need the full virtual address here.
// *** Currently truncate address to 32 bits. This must be changed if // When the TLB's are update it use use the orignal address
// we support larger physical address spaces // *** Currently truncate address to 32 bits. This must be changed if
assign HPTWPAdrE = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]}; // we support larger physical address spaces
assign HPTWPAdrE = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]};
end end
//endgenerate //endgenerate
end else begin end else begin
assign HPTWPAdrE = 0; assign HPTWPAdrE = 0;
assign HPTWTranslate = 0;
assign HPTWReadE = 0; assign HPTWReadE = 0;
assign WalkerInstrPageFaultF = 0; assign WalkerInstrPageFaultF = 0;
assign WalkerLoadPageFaultM = 0; assign WalkerLoadPageFaultM = 0;
assign WalkerStorePageFaultM = 0; assign WalkerStorePageFaultM = 0;
assign SelPTW = 0;
end end
endgenerate endgenerate