Cleanup.

src/ifu/bpred/btb.sv

@@ -51,7 +51,7 @@ module btb #(parameter Depth = 10 ) (
 
   logic [Depth-1:0]         PCNextFIndex, PCFIndex, PCDIndex, PCEIndex, PCMIndex, PCWIndex;
   logic [`XLEN-1:0] 		ResetPC;
-  logic 					MatchF, MatchD, MatchE, MatchM, MatchW, MatchNextX, MatchX;
+  logic 					MatchF, MatchD, MatchE, MatchM, MatchW, MatchX;
   logic [`XLEN+3:0] 		ForwardBTBPrediction, ForwardBTBPredictionF;
   logic [`XLEN+3:0] 		TableBTBPredictionF;
   logic 					UpdateEn;
@@ -80,20 +80,13 @@ module btb #(parameter Depth = 10 ) (
   assign MatchW = PCFIndex == PCWIndex;
   assign MatchX = MatchD | MatchE | MatchM | MatchW;
 
-//  flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
-
   assign ForwardBTBPredictionF = MatchD ? {InstrClassD, BTAD} :
                                 MatchE ? {InstrClassE, IEUAdrE} :
                                 MatchM ? {InstrClassM, IEUAdrM} :
                                 {InstrClassW, IEUAdrW} ;
 
-/* -----\/----- EXCLUDED -----\/-----
-  flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF);
- -----/\----- EXCLUDED -----/\----- */
-
   assign {BTBPredInstrClassF, BTAF} = MatchX ? ForwardBTBPredictionF : {TableBTBPredictionF};
 
-
   assign UpdateEn = |InstrClassM | PredictionInstrClassWrongM;
 
   // An optimization may be using a PC relative address.

src/ifu/bpred/gshare.sv

@@ -43,9 +43,9 @@ module gshare #(parameter k = 10,
 );
 
   logic                    MatchF, MatchD, MatchE, MatchM, MatchW;
-  logic                    MatchX, MatchXF;
+  logic                    MatchX;
 
-  logic [1:0]              TableDirPredictionF, DirPredictionD, DirPredictionE, ForwardNewDirPredictionF, ForwardDirPredictionF;
+  logic [1:0]              TableDirPredictionF, DirPredictionD, DirPredictionE, ForwardNewDirPredictionF;
   logic [1:0]              NewDirPredictionE, NewDirPredictionM, NewDirPredictionW;
 
   logic [k-1:0]            IndexNextF, IndexF, IndexD, IndexE, IndexM, IndexW;
@@ -70,22 +70,17 @@ module gshare #(parameter k = 10,
 
   flopenrc #(k) IndexWReg(clk, reset, FlushW, ~StallW, IndexM, IndexW);
 
-  //assign MatchF = BPBranchF & ~FlushD & (IndexNextF == IndexF);
   assign MatchD = BranchD & ~FlushE & (IndexF == IndexD);
   assign MatchE = BranchE & ~FlushM & (IndexF == IndexE);
   assign MatchM = BranchM & ~FlushW & (IndexF == IndexM);
   assign MatchW = BranchW & ~FlushW & (IndexF == IndexW);
   assign MatchX = MatchD | MatchE | MatchM | MatchW;
 
-//  flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
-
   assign ForwardNewDirPredictionF = MatchD ? {2{DirPredictionD[1]}} :
                                    MatchE ? {NewDirPredictionE} :
                                    MatchM ? {NewDirPredictionM} :
 								   NewDirPredictionW ;
   
-  //flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF);
-
   assign DirPredictionF = MatchX ? ForwardNewDirPredictionF : TableDirPredictionF;
 
   ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),