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Almost fixed issues with irom and dtim address selection.

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This commit is contained in:
Ross Thompson 2022-08-25 15:52:25 -05:00
parent 179aec3616
commit 5c2bc20dbd
2 changed files with 4 additions and 2 deletions
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2
pipelined/src/ifu/ifu.sv
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@ -185,7 +185,7 @@ module ifu (
assign InstrRawF = AllInstrRawF[31:0]; assign InstrRawF = AllInstrRawF[31:0];
if (`IROM) begin : irom if (`IROM) begin : irom
irom irom(.clk, .reset, .Adr(PCNextFSpill), .ReadData(FinalInstrRawF)); irom irom(.clk, .reset, .Adr(CPUBusy | reset ? PCPF : PCNextFSpill), .ReadData(FinalInstrRawF));
assign {BusStall, IFUBusRead} = '0; assign {BusStall, IFUBusRead} = '0;
assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0; assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0;

4
pipelined/src/lsu/lsu.sv
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@ -201,7 +201,9 @@ module lsu (
// *** becomes DTIM_RAM_BASE // *** becomes DTIM_RAM_BASE
if (`DMEM) begin : dtim if (`DMEM) begin : dtim
dtim dtim(.clk, .reset, .LSURWM, .IEUAdrE, .TrapM, .WriteDataM(LSUWriteDataM), dtim dtim(.clk, .reset, .LSURWM,
.IEUAdrE(CPUBusy | LSURWM[0] | reset ? IEUAdrM : IEUAdrE),
.TrapM, .WriteDataM(LSUWriteDataM),
.ReadDataWordM(ReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0]), .Cacheable(CacheableM)); .ReadDataWordM(ReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0]), .Cacheable(CacheableM));
// since we have a local memory the bus connections are all disabled. // since we have a local memory the bus connections are all disabled.