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	added delayed MIP signal
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				@ -38,7 +38,7 @@
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module testbench();
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  parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*8700000; // # of instructions at which to turn on waves in graphical sim
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  parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*3100000; // # of instructions at which to turn on waves in graphical sim
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  string ProgramAddrMapFile, ProgramLabelMapFile;
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  ///////////////////////////////////////////////////////////////////////////////
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@ -137,6 +137,7 @@ module testbench();
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  integer           NumCSRWIndex;
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  integer           NumCSRPostWIndex;
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  logic [`XLEN-1:0] InstrCountW;
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  integer           RequestDelayedMIP;
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  // ------
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  // Macros
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@ -246,9 +247,16 @@ module testbench();
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          MarkerIndex += 2;
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          // match MIP to QEMU's because interrupts are imprecise
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          if(ExpectedCSRArrayM[NumCSRM].substr(0, 2) == "mip") begin
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            $display("%tns: Updating MIP to %x",$time,ExpectedCSRArrayValueM[NumCSRM]);
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            MIPexpected = ExpectedCSRArrayValueM[NumCSRM];
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            force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected;
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            $display("%tn: ExpectedCSRArrayM[7] (MEPC) = %x",$time,ExpectedCSRArrayM[7]);
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            $display("%tn: ExpectedPCM = %x",$time,ExpectedPCM);
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            // if PC does not equal MEPC, request delayed MIP is True
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            if(ExpectedPCM != ExpectedCSRArrayM[7]) begin
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              RequestDelayedMIP = 1;
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            end else begin
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              $display("%tns: Updating MIP to %x",$time,ExpectedCSRArrayValueM[NumCSRM]);
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              MIPexpected = ExpectedCSRArrayValueM[NumCSRM];
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              force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected;
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            end
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          end 
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          NumCSRM++;      
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        end
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@ -326,6 +334,12 @@ module testbench();
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  // step2: make all checks in the write back stage.
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  always @(negedge clk) begin
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    if(RequestDelayedMIP) begin
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      $display("%tns: Updating MIP to %x",$time,ExpectedCSRArrayValueW[NumCSRM]);
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      MIPexpected = ExpectedCSRArrayValueW[NumCSRM];
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      force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected;
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      RequestDelayedMIP = 0;
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    end
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    // always check PC, instruction bits
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    if (checkInstrW) begin
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      InstrCountW += 1;
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